Patents by Inventor Jesse Max GUSS

Jesse Max GUSS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9639494
    Abstract: One embodiment of the present invention includes a hard-coded first device ID. The embodiment also includes a set of fuses that represents a second device ID. The hard-coded device ID and the set of fuses each designate a separate device ID for the device, and each device ID corresponds to a specific operating configuration of the device. The embodiment also includes selection logic to select between the hardcoded device ID and the set of fuses to set the device ID for the device. One advantage of the disclosed embodiments is providing flexibility for engineers who develop the devices while also reducing the likelihood that a third party can counterfeit the device.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: May 2, 2017
    Assignee: NVIDIA Corporation
    Inventors: Jesse Max Guss, Philip Browning Johnson, Chris Marriott, Wojciech Jan Truty
  • Patent number: 9389622
    Abstract: A voltage margin controller, an IC included the same and a method of controlling voltage margin for a voltage domain of an IC are disclosed herein. In one embodiment, the voltage margin controller includes: (1) monitoring branches including circuit function indicators configured to indicate whether circuitry in the voltage domain could operate at corresponding candidate reduced voltage levels and (2) a voltage margin adjuster coupled to the monitoring branches and configured to develop a voltage margin adjustment for a voltage regulator of the voltage domain based upon an operating number of the circuit function indicators.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: July 12, 2016
    Assignee: Nvidia Corporation
    Inventors: Brian L. Smith, Stephen Felix, Jesse Max Guss, Tezaswi Raja
  • Publication number: 20160026195
    Abstract: A voltage margin controller, an IC included the same and a method of controlling voltage margin for a voltage domain of an IC are disclosed herein. In one embodiment, the voltage margin controller includes: (1) monitoring branches including circuit function indicators configured to indicate whether circuitry in the voltage domain could operate at corresponding candidate reduced voltage levels and (2) a voltage margin adjuster coupled to the monitoring branches and configured to develop a voltage margin adjustment for a voltage regulator of the voltage domain based upon an operating number of the circuit function indicators.
    Type: Application
    Filed: October 6, 2015
    Publication date: January 28, 2016
    Inventors: Brian L. Smith, Stephen Felix, Jesse Max Guss, Tezaswi Raja
  • Patent number: 9230678
    Abstract: An enhanced fuseless fuse structure is provided herein. Additionally, an IC with an enhanced fuseless fuse structure, a data structure that can be used with this structure and a method of manufacturing an IC are disclosed herein. In one embodiment, the IC includes: (1) a fuse wrapper configured to decode fuseless fuse data for controlling the fuses, (2) JTAG registers configured to store fuse register values in designated blocks, wherein the fuse register values and the designated blocks are determined from the fuseless fuse data and (3) options registers configurable by software to store fuse override data for modifying the fuse register values.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: January 5, 2016
    Assignee: Nvidia Corporation
    Inventors: Sathish Jothikumar, Jesse Max Guss, Chen Hui
  • Patent number: 9182768
    Abstract: A voltage margin controller, an IC included the same and a method of controlling voltage margin for a voltage domain of an IC are disclosed herein. In one embodiment, the voltage margin controller includes: (1) monitoring branches including circuit function indicators configured to indicate whether circuitry in the voltage domain could operate at corresponding candidate reduced voltage levels and (2) a voltage margin adjuster coupled to the monitoring branches and configured to develop a voltage margin adjustment for a voltage regulator of the voltage domain based upon an operating number of the circuit function indicators.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: November 10, 2015
    Assignee: Nvidia Corporation
    Inventors: Brian L. Smith, Stephen Felix, Jesse Max Guss, Tezaswi Raja
  • Publication number: 20150219697
    Abstract: An integrated circuit (IC) based detection circuit for determining a strap value and a method of detecting a digital strap value. In one embodiment, the detection circuit includes: (1) a first receiver including transistors having first electrical characteristics that define a first threshold for the first receiver, the first receiver operable to generate a first binary digit based on an input signal and the first threshold and (2) a second receiver including transistors having second electrical characteristics that differ from the first electrical characteristics and define a second threshold for the second receiver that is lower than the first threshold, the second receiver operable to generate a second binary digit based on the input signal and the second threshold, the first and second binary digits indicating whether the strap value lies above the first threshold, between the first and second thresholds or below the second threshold.
    Type: Application
    Filed: February 5, 2014
    Publication date: August 6, 2015
    Applicant: Nvidia Corporation
    Inventors: Victor Chen, Jesse Max Guss, Craig Ross, Kevin Wong, Jason Kwok-san Lee
  • Publication number: 20150200020
    Abstract: An enhanced fuseless fuse structure is provided herein. Additionally, an IC with an enhanced fuseless fuse structure, a data structure that can be used with this structure and a method of manufacturing an IC are disclosed herein. In one embodiment, the IC includes: (1) a fuse wrapper configured to decode fuseless fuse data for controlling the fuses, (2) JTAG registers configured to store fuse register values in designated blocks, wherein the fuse register values and the designated blocks are determined from the fuseless fuse data and (3) options registers configurable by software to store fuse override data for modifying the fuse register values.
    Type: Application
    Filed: January 13, 2014
    Publication date: July 16, 2015
    Applicant: Nvidia Corporation
    Inventors: Sathish Jothikumar, Jesse Max Guss, Chen Hui
  • Publication number: 20150192942
    Abstract: A voltage margin controller, an IC included the same and a method of controlling voltage margin for a voltage domain of an IC are disclosed herein. In one embodiment, the voltage margin controller includes: (1) monitoring branches including circuit function indicators configured to indicate whether circuitry in the voltage domain could operate at corresponding candidate reduced voltage levels and (2) a voltage margin adjuster coupled to the monitoring branches and configured to develop a voltage margin adjustment for a voltage regulator of the voltage domain based upon an operating number of the circuit function indicators.
    Type: Application
    Filed: January 8, 2014
    Publication date: July 9, 2015
    Applicant: Nvidia Corporation
    Inventors: Brian L. Smith, Stephen Felix, Jesse Max Guss, Tezaswi Raja
  • Publication number: 20150127860
    Abstract: One embodiment of the present invention includes a hard-coded first device ID. The embodiment also includes a set of fuses that represents a second device ID. The hard-coded device ID and the set of fuses each designate a separate device ID for the device, and each device ID corresponds to a specific operating configuration of the device. The embodiment also includes selection logic to select between the hardcoded device ID and the set of fuses to set the device ID for the device. One advantage of the disclosed embodiments is providing flexibility for engineers who develop the devices while also reducing the likelihood that a third party can counterfeit the device.
    Type: Application
    Filed: November 1, 2013
    Publication date: May 7, 2015
    Applicant: NVIDIA CORPORATION
    Inventors: Jesse Max GUSS, Philip Browning JOHNSON, Chris MARRIOTT, Wojciech Jan TRUTY