Abstract: A PCI host bridge (PHB) includes a warm reset mode and a full reset mode. When a fatal error occurs, the type of fatal error is determined, a reset mode corresponding to that type of fatal error is determined, and a reset corresponding to the reset mode is performed. A full reset clears the error registers, status registers and configuration registers, which then requires the configuration registers to be reconfigured before the PHB can be reinitialized. A warm reset clears the error registers and status registers, but does not clear the configuration registers. A warm reset thus does not require the time to write to the configuration registers, and the PHB can be reinitialized using the existing configuration data in the configuration registers while link training is done in parallel. When initialization of the PHB after a warm reset is not successful, a full reset is performed.

Abstract: Managing a pool of virtual functions including generating a virtual function pool comprising a plurality of virtual functions for at least one single root input/output virtualization (SR-IOV) adapter; creating a control path from a client virtual network interface controller (VNIC) driver in a first client partition to a target network using an active virtual function; receiving a failure alert indicating that the control path from the client VNIC driver in the first client partition to the target network using the active virtual function has failed; selecting, from the virtual function pool, a backup virtual function for the first client partition based on the failure alert; and recreating the control path from the client VNIC driver in the first client partition to the target network using the backup virtual function.

Abstract: A method, system and computer program product are provided for detecting state and sparing of optical Peripheral Component Interconnect Express (PCI-Express or PCIE) cable channels attached to an IO drawer. System firmware is provided for implementing health check functions and state detection and sparing functions. One or more optical cables are connected between a host bridge and an PCIE enclosure, each optical cable includes one or more spare optical channels. An identified failed optical channel is rerouted to the spare optical channel.

Abstract: Managing flexible adapter configurations in a computer system including assigning an initial amount of resources to a set of empty expansion bus slots of the computer system; detecting an adapter has been attached to one of the set of empty expansion bus slots; receiving, by a hypervisor, a request for additional resources for use by the detected adapter, wherein the additional resources are in addition to the initial amount of resources assigned to the expansion bus slot occupied by the detected adapter; determining, by the hypervisor, an availability of the additional resources for the detected adapter; in response to determining that the additional resources are available for the detected adapter, assigning, by the hypervisor at runtime, the requested additional resources to the detected adapter.

Abstract: Live partition mobility in a computing environment that includes a source system and a target system may be carried out by: pausing a logical partition on the source system, wherein the logical partition is mapped to an I/O adapter of the source system; copying, to the target system, configuration information describing the mapping of the logical partition to the I/O adapter; copying, to the target system, the logical partition of the source system; placing an I/O adapter of the target system into an error state; mapping, in dependence upon the configuration information, the logical partition of the target system to the I/O adapter of the target system; placing the I/O adapter of the target system into an error recovery state; and resuming the logical partition on the target system.

Abstract: The present disclosure relates to sharing an I/O device across multiple virtual machines. According to one embodiment, a computing system configures shared ownership of the I/O device between a first partition and one or more of the plurality of virtual machines. The computing system transfers partial ownership of the I/O device from the first partition to the one or more virtual machines and generates device configuration information for the I/O device. The virtual machines can use the generated device configuration information to access and configure the I/O device. Once the I/O device is configured for shared ownership, the computing system boots the one or more virtual machines.

Abstract: Failover of a virtual function exposed by an SR-IOV adapter of a computing system, including: instantiating, by a hypervisor, a standby virtual function in the computing system; detecting a loss of communication between a logical partition and an active virtual function mapped to the logical partition; placing the active virtual function and the standby virtual function in an error state; remapping the logical partition to the standby virtual function; and placing the standby virtual function in an error recovery state.

Abstract: Managing flexible adapter configurations in a computer system including assigning an initial amount of resources to a set of empty expansion bus slots of the computer system; detecting an adapter has been attached to one of the set of empty expansion bus slots; receiving, by a hypervisor, a request for additional resources for use by the detected adapter, wherein the additional resources are in addition to the initial amount of resources assigned to the expansion bus slot occupied by the detected adapter; determining, by the hypervisor, an availability of the additional resources for the detected adapter; in response to determining that the additional resources are available for the detected adapter, assigning, by the hypervisor at runtime, the requested additional resources to the detected adapter.

Abstract: A PCI host bridge (PHB) includes a warm reset mode and a full reset mode. When a fatal error occurs, the type of fatal error is determined, a reset mode corresponding to that type of fatal error is determined, and a reset corresponding to the reset mode is performed. A full reset clears the error registers, status registers and configuration registers, which then requires the configuration registers to be reconfigured before the PHB can be reinitialized. A warm reset clears the error registers and status registers, but does not clear the configuration registers. A warm reset thus does not require the time to write to the configuration registers, and the PHB can be reinitialized using the existing configuration data in the configuration registers while link training is done in parallel. When initialization of the PHB after a warm reset is not successful, a full reset is performed.

Abstract: Managing flexible adapter configurations in a computer system including assigning an initial amount of resources to a set of empty expansion bus slots of the computer system; detecting an adapter has been attached to one of the set of empty expansion bus slots; receiving, by a hypervisor, a request for additional resources for use by the detected adapter, wherein the additional resources are in addition to the initial amount of resources assigned to the expansion bus slot occupied by the detected adapter; determining, by the hypervisor, an availability of the additional resources for the detected adapter; in response to determining that the additional resources are available for the detected adapter, assigning, by the hypervisor at runtime, the requested additional resources to the detected adapter.

Abstract: Managing a pool of virtual functions including generating a virtual function pool comprising a plurality of virtual functions for at least one single root input/output virtualization (SR-IOV) adapter; creating a control path from a client virtual network interface controller (VNIC) driver in a first client partition to a target network using an active virtual function; receiving a failure alert indicating that the control path from the client VNIC driver in the first client partition to the target network using the active virtual function has failed; selecting, from the virtual function pool, a backup virtual function for the first client partition based on the failure alert; and recreating the control path from the client VNIC driver in the first client partition to the target network using the backup virtual function.

Abstract: A PCI host bridge (PHB) includes a warm reset mode and a full reset mode. When a fatal error occurs, the type of fatal error is determined, a reset mode corresponding to that type of fatal error is determined, and a reset corresponding to the reset mode is performed. A full reset clears the error registers, status registers and configuration registers, which then requires the configuration registers to be reconfigured before the PHB can be reinitialized. A warm reset clears the error registers and status registers, but does not clear the configuration registers. A warm reset thus does not require the time to write to the configuration registers, and the PHB can be reinitialized using the existing configuration data in the configuration registers while link training is done in parallel. When initialization of the PHB after a warm reset is not successful, a full reset is performed.

Abstract: A method, system and computer program product are provided for implementing cable failover in multiple cable Peripheral Component Interconnect Express (PCIE) IO interconnections to an external IO enclosure. System firmware is provided for implementing health check functions for the PCIE IO interconnections to identify a faulted low byte cable. A cable failover mechanism recovers a PCI link to the external IO enclosure. A multiplexer logic is provided between the PCIE host bridge (PHB) and the cable connected to the IO enclosure to perform a full lane reversal of the PCIE lanes.

Abstract: A method, system and computer program product are provided for implementing cable failover in multiple cable Peripheral Component Interconnect Express (PCIE) IO interconnections to an external IO enclosure. System firmware is provided for implementing health check functions for the PCIE IO interconnections to identify a faulted low byte cable. A cable failover mechanism recovers a PCI link to the external IO enclosure. A multiplexer logic is provided between the PCIE host bridge (PHB) and the cable connected to the IO enclosure to perform a full lane reversal of the PCIE lanes.

Abstract: According to an embodiment, a system, a method, and/or a computer program product is provided to allow a choice of allocating resources of a processor host bridge (PHB) at initial setup of a computer system to a group of peripheral component interconnect express (PCI-E) slots via a PCI-E switch, or alternatively to allocate resources of the PHB directly to a single PCI-E slot. The system may include a PHB, a first switch connected to the PHB, where the first switch is a simple circuit, a second switch connected to the first switch, where the second switch is a simple circuit, a PCI-E switch connected to the first switch and connected to the second switch, and a first PCI-E slot connected to the second switch.

Abstract: Migrating interrupts from a source I/O adapter of a computing system to a destination I/O adapter of the computing system, includes: collecting, by a hypervisor of the computing system, interrupt mapping information, where the hypervisor supports operation of a logical partition executing and the logical partition is configured to receive interrupts from the source I/O adapter; configuring, by the hypervisor, the destination I/O adapter with the interrupt mapping information collected by the hypervisor; placing, by the hypervisor, the destination I/O adapter and the source I/O in an error state; deconfiguring the source I/O adapter from the logical partition; and enabling the logical partition and destination I/O adapter to recover from the error state.

Abstract: According to an embodiment, a system, a method, and/or a computer program product is provided to allow a choice of allocating resources of a processor host bridge (PHB) at initial setup of a computer system to a group of peripheral component interconnect express (PCI-E) slots via a PCI-E switch, or alternatively to allocate resources of the PHB directly to a single PCI-E slot. The system may include a PHB, a first switch connected to the PHB, where the first switch is a simple circuit, a second switch connected to the first switch, where the second switch is a simple circuit, a PCI-E switch connected to the first switch and connected to the second switch, and a first PCI-E slot connected to the second switch.

Abstract: Dynamically bypassing a peripheral component interconnect (PCI) switch including preparing, during run time, a PCI host bridge for disconnection from the PCI switch, wherein the PCI host bridge is connected to a first PCI slot via the PCI switch; toggling, during run time, an electrical switch, wherein toggling the electrical switch bypasses the PCI switch and creates a direct connection between the PCI host bridge and the first PCI slot; and configuring, during run time, the PCI host bridge for the direct connection between the PCI host bridge and the first PCI slot.

Abstract: Systems, methods, and computer program products to perform an operation comprising executing a device driver in a private logical partition on a compute host, wherein the device driver is configured to execute in an environment different than an environment of a hypervisor of the compute host, establishing a communication channel between the private logical partition and an adjunct partition executing on the compute host, and configuring, responsive to a command sent by the adjunct partition to the device driver via the communication channel, a physical function of a single root I/O virtualization (SR-IOV) device of the host system.

Abstract: A method to manage peripheral component interconnect (PCI) memory includes accessing a page table that includes mapped data representing base address register (BAR) space and addresses of PCI devices. The method also includes determining whether a requested address of a PCI device has a corresponding entry in the page table. The method further includes invoking a hypervisor to perform a memory operation to obtain address information of the PCI device upon determining that the requested address does not have the corresponding entry in the page table.