Abstract: A method for processing design data for a semiconductor circuit may be provided. The design data describe a signal line and related physical characteristics. The method comprises receiving the design data for the signal line, receiving constraint data describing a blockage area, and determining a segment of the signal line that would overlap with the blockage area assuming a direct path from the source to the sink. The method comprises further determining for the segment, based on the length of the segment, whether the segment is route-able without inserting a buffer while meeting the timing constraints, and modifying, in case a segment is not route-able without inserting a buffer, the physical characteristics of the signal line. Thereby, the determining the segment, the determining whether the segment length is route-able, and the modifying the physical characteristics is performed before placing buffers in the signal line and routing the signal line.

Abstract: A method for processing design data for a semiconductor circuit may be provided. The design data describe a signal line and related physical characteristics. The method comprises receiving the design data for the signal line, receiving constraint data describing a blockage area, and determining a segment of the signal line that would overlap with the blockage area assuming a direct path from the source to the sink. The method comprises further determining for the segment, based on the length of the segment, whether the segment is route-able without inserting a buffer while meeting the timing constraints, and modifying, in case a segment is not route-able without inserting a buffer, the physical characteristics of the signal line. Thereby, the determining the segment, the determining whether the segment length is route-able, and the modifying the physical characteristics is performed before placing buffers in the signal line and routing the signal line.

Abstract: A method for assigning nets to wiring planes for generating a chip design includes executing, by a computer, a zero wire load timing session for a placed but unbufferred chip design. All nets of the chip design are set to a single wide wiring track without wiring plane assignments. A delta time delay is added to each sink of each of the nets to represent an estimated time of flight (TOF) delay. The nets wiring plane or width type for a particular pin is upgraded to a type having improved TOF characteristics. Each of the nets are compared against new predetermined slack and distance targets and new assigned wiring plane or width type determined to consume additional wiring track resources, and based on results, the upgrade is repeated or a design for session timing state for the nets is output to represent the unbufferred chip design.

Abstract: A first open path in a microprocessor design is identified. At least one modification to a design of that first open path is simulated. An updated arrival time at a pin is calculated based on the simulated modification or modifications. An updated path time is then calculated based on the updated arrival time.

Abstract: A first open path in a microprocessor design is identified. At least one modification to a design of that first open path is simulated. An updated arrival time at a pin is calculated based on the simulated modification or modifications. An updated path time is then calculated based on the updated arrival time.

Abstract: A method for assigning nets to wiring planes for generating a chip design includes executing, by a computer, a zero wire load timing session for a placed but unbufferred chip design. All nets of the chip design are set to a single wide wiring track without wiring plane assignments. A delta time delay is added to each sink of each of the nets to represent an estimated time of flight (TOF) delay. The nets wiring plane or width type for a particular pin is upgraded to a type having improved TOF characteristics. Each of the nets are compared against new predetermined slack and distance targets and new assigned wiring plane or width type determined to consume additional wiring track resources, and based on results, the upgrade is repeated or a design for session timing state for the nets is output to represent the unbufferred chip design.

Abstract: Nets are assigned to wiring planes for generating a chip design. A computer is caused to execute a zero wire load timing session for a placed but unbufferred chip design. All nets of the chip design are set to a single wide wiring track without wiring plane assignments. A delta time delay is added to each sink of each of the nets to represent an estimated time of flight (TOF) delay. The nets wiring plane or width type for a particular pin is upgraded to a type having improved TOF characteristics. Each of the nets are compared against new predetermined slack and distance targets and new assigned wiring plane or width type determined to consume additional wiring track resources, and based on results, the upgrade is repeated or a design for session timing state for the nets is output to represent the unbufferred chip design.

Abstract: A first open path in a microprocessor design is identified. At least one modification to a design of that first open path is simulated. An updated arrival time at a pin is calculated based on the simulated modification or modifications. An updated path time is then calculated based on the updated arrival time.

Abstract: A first open path in a microprocessor design is identified. At least one modification to a design of that first open path is simulated. An updated arrival time at a pin is calculated based on the simulated modification or modifications. An updated path time is then calculated based on the updated arrival time.