Patents by Inventor Jesse Phou

Jesse Phou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR DEVICE WITH BOND AND PROBE PADS
    Publication number: 20140332811
    Abstract: A semiconductor die has an active face with an arrangement of I/O pads around its edges. The I/O pads include bond pads and probe pads. Two types of I/O pads are provided and the two types of pads are arranged in a staggered arrangement around the edges of the die. The first type of I/O pad has bond pads that are spaced from the probe pads and connected with an interconnecting member. The second type of I/O pads has bond pads that are adjacent to and abutting probe pads. Providing two types of I/O pads and the staggered arrangement of the I/O pads reduces the area of the I/O pads and underlying I/O regions, which saves core area of the die.
    Type: Application
    Filed: May 12, 2013
    Publication date: November 13, 2014
    Inventors: Naveen Kumar, Gurinder Singh Baghria, Rishi Bhooshan, Jesse Phou
  • Stackable molded packages and methods of making the same
    Patent number: 8044494
    Abstract: A first packaged integrated circuit (IC) includes a package substrate, at least one IC die attached to a first surface of the package substrate, a plurality of conductive members on the first surface at least partially surrounding the at least one IC die and electrically connected to the at least one IC die, an encapsulant over the first surface surrounding the at least one IC die and the plurality of conductive members, wherein at least a portion of each of the plurality of conductive members is exposed by the encapsulant. A second packaged IC may be stacked onto the first packaged IC. The second packaged IC includes at least one IC die and a plurality of conductive members, each conductive member of the plurality of conductive members of the second packaged IC is in contact with a corresponding conductive member of the plurality conductive members of the first packaged IC.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: October 25, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Addi B. Mistry, Marc A. Mangrum, David T. Patten, Jesse Phou, Ziep Tran
  • STACKABLE MOLDED PACKAGES AND METHODS OF MAKING THE SAME
    Publication number: 20100013065
    Abstract: A first packaged integrated circuit (IC) includes a package substrate, at least one IC die attached to a first surface of the package substrate, a plurality of conductive members on the first surface at least partially surrounding the at least one IC die and electrically connected to the at least one IC die, an encapsulant over the first surface surrounding the at least one IC die and the plurality of conductive members, wherein at least a portion of each of the plurality of conductive members is exposed by the encapsulant. A second packaged IC may be stacked onto the first packaged IC. The second packaged IC includes at least one IC die and a plurality of conductive members, each conductive member of the plurality of conductive members of the second packaged IC is in contact with a corresponding conductive member of the plurality conductive members of the first packaged IC.
    Type: Application
    Filed: September 25, 2009
    Publication date: January 21, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Addi B. Mistry, Marc A. Mangrum, David T. Patten, Jesse Phou, Ziep Tran
  • STACKABLE MOLDED PACKAGES AND METHODS OF MAKING THE SAME
    Publication number: 20080108179
    Abstract: A first packaged integrated circuit (IC) includes a package substrate, at least one IC die attached to a first surface of the package substrate, a plurality of conductive members on the first surface at least partially surrounding the at least one IC die and electrically connected to the at least one IC die, an encapsulant over the first surface surrounding the at least one IC die and the plurality of conductive members, wherein at least a portion of each of the plurality of conductive members is exposed by the encapsulant. A second packaged IC may be stacked onto the first packaged IC. The second packaged IC includes at least one IC die and a plurality of conductive members, each conductive member of the plurality of conductive members of the second packaged IC is in contact with a corresponding conductive member of the plurality conductive members of the first packaged IC.
    Type: Application
    Filed: January 3, 2008
    Publication date: May 8, 2008
    Applicant: Freescale Semiconductor, Inc
    Inventors: Addi Mistry, Marc Mangrum, David Patten, Jesse Phou, Ziep Tran
  • Stackable molded packages and methods of making the same
    Publication number: 20070141751
    Abstract: A first packaged integrated circuit (IC) includes a package substrate, at least one IC die attached to a first surface of the package substrate, a plurality of conductive members on the first surface at least partially surrounding the at least one IC die and electrically connected to the at least one IC die, an encapsulant over the first surface surrounding the at least one IC die and the plurality of conductive members, wherein at least a portion of each of the plurality of conductive members is exposed by the encapsulant. A second packaged IC may be stacked onto the first packaged IC. The second packaged IC includes at least one IC die and a plurality of conductive members, each conductive member of the plurality of conductive members of the second packaged IC is in contact with a corresponding conductive member of the plurality conductive members of the first packaged IC.
    Type: Application
    Filed: December 16, 2005
    Publication date: June 21, 2007
    Inventors: Addi Mistry, Marc Mangrum, David Patten, Jesse Phou, Ziep Tran