Abstract: Electronic systems for promotional offers are disclosed. An illustrative electronic system may include a computing device and a storage medium. The storage medium may contain one or more programming instructions that, when executed, cause the computing device to generate scores for customers from a customer database for distribution of limited quantities of promotional offers. Each score may be associated with one customer and one promotional offer, and each score may measure a probability that the associated customer will make a purchase in accordance with the associated offer. The programming instructions may further cause the computing device to identify a highest score, determine a customer associated with the highest score, determine a promotional offer associated with the highest score, assign the promotional offer to a personalized offer list for the customer if the promotional offer satisfies one or more constraints.

Abstract: Electronic systems for promotional offers are disclosed. An illustrative electronic system may include a computing device and a storage medium. The storage medium may contain one or more programming instructions that, when executed, cause the computing device to generate scores for customers from a customer database for distribution of limited quantities of promotional offers. Each score may be associated with one customer and one promotional offer, and each score may measure a probability that the associated customer will make a purchase in accordance with the associated offer. The programming instructions may further cause the computing device to identify a highest score, determine a customer associated with the highest score, determine a promotional offer associated with the highest score, assign the promotional offer to a personalized offer list for the customer if the promotional offer satisfies one or more constraints.

Abstract: A system for distributing limited numbers of promotional offers to individual customers, the promotional offers being targeted to customers based on the customers' individual probabilities of accepting the offers in such a way that each customer can receive a limited number of offers that are estimated to be most likely to be acceptable by the customer. Customer-Based targeting analyzes each customer's past purchasing behavior relative to a master list of promotional offers made available to all customers. From that master list Customer-Based targeting selects a preset limit of promotional offers for each individual customer according to the likelihood that, given the opportunity to select any offers of the master list, each customer would prefer those few offers selected specifically for the customer. Various techniques are disclosed for providing an offer acceptance probability profile tailored for individual customers for use in the Customer-Based targeting technique.

Abstract: A system for distributing limited numbers of promotional offers targeted to individual customers based on the customers' individual probabilities of accepting the offers is disclosed. Each customer can receive a limited number of offers estimated to be most likely to be acceptable by the customer. Customer-Based targeting analyzes each customer's past purchasing behavior relative to a master list of promotional offers made available to all customers and selects a number of promotional offers most likely to be preferred by each customer. Various techniques, such as empirical Bayes techniques and sparse data handling techniques, are disclosed for providing an offer acceptance probability profile tailored for individual customers. Product groupings and market segments are taken into account. Various marketing strategies are incorporated into the system.

Abstract: A programmable controller architecture utilizes specialized processors in a co-processing system so that each function is optimized. The system comprises first and second processors having respective instruction sets and respective associated means for fetching instructions from a common memory. Each of the processors and its instruction set is tailored to a corresponding processor's specialized function. Each processor's instruction set includes a subset of special instructions, the occurrence of one of which signifies that control is to be passed from one processor to the other. Upon encountering a special instruction within its special instruction subset, a given processor invokes associated control passing circuitry for suspending its own operation and commencing the operation of the other processor. The passage of control occurs very quickly so that the speed benefits of switching control are not lost in the overhead of such switching.

Abstract: An input/output device monitors the transmission of information between a processor of a programmable controller and sensors and actuators of a process to be controlled. This device includes electronic circuits adapted for calculating the parities of the digital words which pass therethrough, these parities being compared with corresponding parities calculated by the processor which thereafter invalidates the words having two different parities.

Abstract: An input/output device is used for a programmable controller having on input/output cards a plurality of electronic channels forming the logic interfaces between the connection bus with the central unit and the sensors or the actuators connected to the controllers; this device further uses electronic circuits for monitoring the good transmission of input/output signals by the adaptation interfaces providing for the galvanic isolation of the bus with respect to the sensors and actuators of the controlled automatism.

Abstract: A very fast and efficient Boolean processor ("BP") (20) capable of compiling a full range of diagrams or expressions in ladder, logigram, and Boolean with a small but powerful instruction set. The BP includes an instruction decoder (34), combinatoric logic (35), a T-register (42) which holds the temporary results of a sequential AND operation, an N-register (43) which holds the initial Boolean value of T, a Binary Accumulator Memory ("BAM") (40) which is used as a scratchpad for a program which evaluates a ladder or logigram diagram or a Boolean expression, a source address ("S") in BAM (40) from which an initial operand is taken, a destination address ("D") in BAM (40) in which the result of an operation is stored, and a destination address register ("DAR") (45) in which the destination address is stored. The instruction set includes a subset of input instructions and a subset of structure instructions. The operand (I) of an input instruction is an address in IOIM (25).

Abstract: An interconnecting transparent serial bus for extending a parallel CPU domain to a parallel peripheral module domain includes a bidirectional serial protocol for transferring information between the CPU and one or more peripheral module controllers, referred to as rack masters. Each rack master provides a parallel path to any number of peripheral modules associated therewith. Serial bus protocol includes a frame line, defining a synchronous information exchange interval; a clock line, for propagating a synchronous information clock signal during the information exchange interval; a sync line, for propagating a sync signal to identify one or more discrete asynchronous information fields during the information exchange interval; and a signal line for propagating data, address, and control information between the CPU and its associated rack masters in serial fashion.

Abstract: A microcomputerized postage meter that provides high degrees of security and fault tolerance. The meter maintains data security under low power conditions by the use of functionally nonvolatile memory units. Register and other data which must survive normal and abnormal losses of power to the meter electronics are stored in dual redundant battery augmented memories (hereinafter designated BAMs). Upon detecting an error condition, the microcomputer writes an appropriate fault code to the BAMs. A mechanism for disabling the meter includes dual redundant flip-flops which are set to a "faulted" state upon detection by the microcomputer of a failure condition. These flip-flops are powered by the BAM batteries. They cannot be reset except by physical access to the meter interior, which access is only available to authorized personnel at the factory. The fault flip-flops are also set when the microcomputer fails to properly execute its own operating program.