Abstract: A silicon carbide metal semiconductor field-effect transistor includes a bi-layer silicon carbide buffer for improving electron confinement in the channel region and/or a layer disposed over at least the channel region of the transistor for suppressing surface effects caused by dangling bonds and interface states. Also, a sloped MESA fabrication method which utilizes a dielectric etch mask that protects the MESA top surface during MESA processing and enables formation of sloped MESA sidewalls.

Abstract: A silicon carbide metal semiconductor field-effect transistor includes a bi-layer silicon carbide buffer for improving electron confinement in the channel region and/or a layer disposed over at least the channel region of the transistor for suppressing surface effects caused by dangling bonds and interface states. Also, a sloped MESA fabrication method which utilizes a dielectric etch mask that protects the MESA top surface during MESA processing and enables formation of sloped MESA sidewalls.

Abstract: A silicon carbide metal semiconductor field-effect transistor includes a bi-layer silicon carbide buffer for improving electron confinement in the channel region and/or a layer disposed over at least the channel region of the transistor for suppressing surface effects caused by dangling bonds and interface states. Also, a sloped MESA fabrication method which utilizes a dielectric etch mask that protects the MESA top surface during MESA processing and enables formation of sloped MESA sidewalls.

Abstract: A method of forming a self-aligned protective layer within a UMOSFET device includes forming a trench within an upper surface of a drift layer, the drift layer of a first polarity type, and epitaxially growing a protective layer on a bottom surface of the trench, the protective layer comprising dopant of the second polarity type. The protective layer is disposed beneath a gate insulating layer formed thereupon.

Abstract: A method of forming a channel in a semiconductor device including forming an opening in a masking layer to expose a portion of an underlying semiconductor layer through the opening is provided. The method further includes disposing a screening layer and implanting a first type of ions in the portion of the underlying semiconductor layer through the screening layer and through the opening in the masking layer. A second type of ions are implanted in the portion of the underlying semiconductor layer through the screening layer and through the opening in the masking layer at an oblique ion implantation angle wherein a lateral spread of second type ions is greater than a lateral spread of first type ions. Semiconductor devices fabricated in accordance to above said method is also provided.

Abstract: A method of processing a semiconductor substrate is provided. The method includes depositing an amorphous hydrogenated carbon film on a semiconductor substrate using a low temperature plasma deposition process and performing at least one high temperature processing step on the semiconductor substrate. The SiC substrate is processed by ion implanting at least one dopant species into at least one selected region of the SiC substrate, depositing a amorphous hydrogenated carbon film on the SiC substrate using a plasma enhanced chemical vapor deposition (PECVD) process, performing at least one high temperature processing step on the SiC substrate and removing the amorphous hydrogenated carbon film after performing the high temperature processing step.

Abstract: A gas sensor device including a semiconductor substrate; one or more catalytic gate-electrodes deposited on a surface of the semiconductor substrate; one or more ohmic contacts deposited on the surface of the semiconductor substrate and a passivation layer deposited on at least a portion of the surface; wherein the semiconductor substrate includes a material selected from the group consisting of silicon carbide, diamond, Group III nitrides, alloys of Group III nitrides, zinc oxide, and any combinations thereof.

Abstract: A silicon carbide metal semiconductor field-effect transistor includes a bi-layer silicon carbide buffer for improving electron confinement in the channel region and/or a layer disposed over at least the channel region of the transistor for suppressing surface effects caused by dangling bonds and interface states. Also, a sloped MESA fabrication method which utilizes a dielectric etch mask that protects the MESA top surface during MESA processing and enables formation of sloped MESA sidewalls.

Abstract: A gas sensor device including a semiconductor substrate; one or more catalytic gate-electrodes deposited on a surface of the semiconductor substrate; one or more ohmic contacts deposited on the surface of the semiconductor substrate and a passivation layer deposited on at least a portion of the surface; wherein the semiconductor substrate includes a material selected from the group consisting of silicon carbide, diamond, Group III nitrides, alloys of Group III nitrides, zinc oxide, and any combinations thereof.