Patents by Inventor Jessica A. Levy

Jessica A. Levy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Through silicon via wafer and methods of manufacturing
    Patent number: 9041210
    Abstract: A through silicon via with sidewall roughness and methods of manufacturing the same are disclosed. The method includes forming a via in a substrate and roughening a sidewall of the via by depositing material within the via. The method further includes removing a backside of the substrate to form a through via with a roughened sidewall structure.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: May 26, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey P. Gambino, Jessica A. Levy, Cameron E. Luce, Daniel S. Vanslette, Bucknell C. Webb
  • Transistor and method of forming the transistor so as to have reduced base resistance
    Patent number: 8846481
    Abstract: Disclosed is a transistor structure, having a completely silicided extrinsic base for reduced base resistance Rb. Specifically, a metal silicide layer covers the extrinsic base, including the portion of the extrinsic base that extends below the upper portion of a T-shaped emitter. One exemplary technique for ensuring that the metal silicide layer covers this portion of the extrinsic base requires tapering the upper portion of the emitter. Such tapering allows a sacrificial layer below the upper portion of the emitter to be completely removed during processing, thereby exposing the extrinsic base below and allowing the metal layer required for silicidation to be deposited thereon. This metal layer can be deposited, for example, using a high pressure sputtering technique to ensure that all exposed surfaces of the extrinsic base, even those below the upper portion of the emitter, are covered.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: September 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Marc W. Cantell, Thai Doan, Jessica A. Levy, Qizhi Liu, William J. Murphy, Christa R. Willets
  • TRANSISTOR AND METHOD OF FORMING THE TRANSISTOR SO AS TO HAVE REDUCED BASE RESISTANCE
    Publication number: 20140113426
    Abstract: Disclosed is a transistor structure, having a completely silicided extrinsic base for reduced base resistance Rb. Specifically, a metal silicide layer covers the extrinsic base, including the portion of the extrinsic base that extends below the upper portion of a T-shaped emitter. One exemplary technique for ensuring that the metal silicide layer covers this portion of the extrinsic base requires tapering the upper portion of the emitter. Such tapering allows a sacrificial layer below the upper portion of the emitter to be completely removed during processing, thereby exposing the extrinsic base below and allowing the metal layer required for silicidation to be deposited thereon. This metal layer can be deposited, for example, using a high pressure sputtering technique to ensure that all exposed surfaces of the extrinsic base, even those below the upper portion of the emitter, are covered.
    Type: Application
    Filed: December 20, 2013
    Publication date: April 24, 2014
    Applicant: International Business Machines Corporation
    Inventors: Marc W. Cantell, Thai Doan, Jessica A. Levy, Qizhi Liu, William J. Murphy, Christa R. Willets
  • THROUGH SILICON VIA WAFER AND METHODS OF MANUFACTURING
    Publication number: 20130334701
    Abstract: A through silicon via with sidewall roughness and methods of manufacturing the same are disclosed. The method includes forming a via in a substrate and roughening a sidewall of the via by depositing material within the via. The method further includes removing a backside of the substrate to form a through via with a roughened sidewall structure.
    Type: Application
    Filed: June 19, 2012
    Publication date: December 19, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey P. GAMBINO, Jessica A. LEVY, Cameron E. LUCE, Daniel S. VANSLETTE, Bucknell C. WEBB
  • TRANSISTOR AND METHOD OF FORMING THE TRANSISTOR SO AS TO HAVE REDUCED BASE RESISTANCE
    Publication number: 20120313146
    Abstract: Disclosed is a transistor structure, having a completely silicided extrinsic base for reduced base resistance Rb. Specifically, a metal silicide layer covers the extrinsic base, including the portion of the extrinsic base that extends below the upper portion of a T-shaped emitter. One exemplary technique for ensuring that the metal silicide layer covers this portion of the extrinsic base requires tapering the upper portion of the emitter. Such tapering allows a sacrificial layer below the upper portion of the emitter to be completely removed during processing, thereby exposing the extrinsic base below and allowing the metal layer required for silicidation to be deposited thereon. This metal layer can be deposited, for example, using a high pressure sputtering technique to ensure that all exposed surfaces of the extrinsic base, even those below the upper portion of the emitter, are covered.
    Type: Application
    Filed: June 8, 2011
    Publication date: December 13, 2012
    Applicant: International Business Machines Corporation
    Inventors: Marc W. Cantell, Thai Doan, Jessica A. Levy, Qizhi Liu, William J. Murphy, Christa R. Willets