Patents by Inventor Jessica Dechene
Jessica Dechene has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11837501Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.Type: GrantFiled: January 10, 2022Date of Patent: December 5, 2023Assignee: TESSERA LLCInventors: Benjamin D. Briggs, Jessica Dechene, Elbert Huang, Joe Lee, Theodorus E. Standaert
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Publication number: 20220181205Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.Type: ApplicationFiled: January 10, 2022Publication date: June 9, 2022Inventors: Benjamin D. Briggs, Jessica Dechene, Elbert Huang, Joe Lee, Theodorus E. Standaert
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Patent number: 11257717Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.Type: GrantFiled: November 9, 2020Date of Patent: February 22, 2022Assignee: Tessera, Inc.Inventors: Benjamin D. Briggs, Jessica Dechene, Elbert E. Huang, Joe Lee, Theodorus E. Standaert
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Publication number: 20210082758Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.Type: ApplicationFiled: November 9, 2020Publication date: March 18, 2021Inventors: Benjamin D. Briggs, Jessica Dechene, Elbert E. Huang, Joe Lee, Theodorus E. Standaert
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Patent number: 10832952Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.Type: GrantFiled: June 21, 2018Date of Patent: November 10, 2020Assignee: Tessera, Inc.Inventors: Benjamin D. Briggs, Jessica Dechene, Elbert E. Huang, Joe Lee, Theodorus E. Standaert
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Patent number: 10833160Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. A sidewall spacer is arranged adjacent to a sidewall of a gate electrode, a source/drain region is arranged laterally adjacent to the sidewall spacer, and a contact is arranged over the source/drain region and laterally adjacent to the sidewall spacer. The contact is coupled with the source/drain region. A section of an interlayer dielectric layer is laterally arranged between the contact and the sidewall spacer.Type: GrantFiled: April 17, 2019Date of Patent: November 10, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Michael Aquilino, Daniel Jaeger, Naved Siddiqui, Jessica Dechene, Daniel J. Dechene, Shreesh Narasimha, Natalia Borjemscaia
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Publication number: 20200335591Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. A sidewall spacer is arranged adjacent to a sidewall of a gate electrode, a source/drain region is arranged laterally adjacent to the sidewall spacer, and a contact is arranged over the source/drain region and laterally adjacent to the sidewall spacer. The contact is coupled with the source/drain region. A section of an interlayer dielectric layer is laterally arranged between the contact and the sidewall spacer.Type: ApplicationFiled: April 17, 2019Publication date: October 22, 2020Inventors: Michael Aquilino, Daniel Jaeger, Naved Siddiqui, Jessica Dechene, Daniel J. Dechene, Shreesh Narasimha, Natalia Borjemscaia
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Patent number: 10636706Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.Type: GrantFiled: June 21, 2018Date of Patent: April 28, 2020Assignee: Tessera, Inc.Inventors: Benjamin D. Briggs, Jessica Dechene, Elbert E. Huang, Joe Lee, Theodorus E. Standaert
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Patent number: 10586733Abstract: An upper layer is formed in a first interlayer dielectric (ILD) layer. The upper layer comprises a plurality of metal interconnects and one or more upper layer air gaps positioned between adjacent metal interconnects. A lower layer is formed in the first ILD layer. The lower layer comprises one or more vias, and one or more lower air gaps positioned between adjacent vias. The upper layer and the lower layer are formed in accordance with a dual-damascene process.Type: GrantFiled: January 2, 2019Date of Patent: March 10, 2020Assignee: International Business Machines CorporationInventors: Richard A. Conti, Jessica Dechene, Susan S. Fan, Son V. Nguyen, Jeffrey C. Shearer
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Patent number: 10453751Abstract: A tone inversion method for integrated circuit (IC) fabrication includes providing a substrate with a layer of amorphous carbon over the substrate and a patterning layer over the amorphous carbon layer. The patterning layer is etched to define a first pattern of raised structures and a complementary recessed pattern that is filled with a layer of image reverse material. The first pattern of raised structures is then removed to define a second pattern of structures comprising the image reverse material. A selective etching step is used to transfer the second pattern into a dielectric layer disposed between the layer of amorphous carbon and the substrate.Type: GrantFiled: February 14, 2017Date of Patent: October 22, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Xiaofeng Qiu, Michael V. Aquilino, Patrick D. Carpenter, Jessica Dechene, Ming Hao Tang, Haigou Huang, Huy Cao
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Patent number: 10325819Abstract: At least one method, apparatus and system disclosed herein involves forming trench silicide region contact. A plurality of fins are formed on a semiconductor substrate. An epitaxial (EPI) feature is formed at a top portion of each fin of the first portion over a first portion of the fins. A gate region is formed over a second portion of the fins. A trench is formed in a portion of the gate region. A void is formed adjacent the a portion of the gate region. A first silicon feature is formed in the trench. A second silicon feature is formed in the void. Subsequently, a replacement metal gate (RMG) process is performed in the gate region. A TS cut region is formed over the trench. The first silicon feature and the second silicon feature are removed. A metallization process is performed in the void to form a contact.Type: GrantFiled: March 13, 2018Date of Patent: June 18, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Jinsheng Gao, Daniel Jaeger, Michael Aquilino, Patrick Carpenter, Jessica Dechene, Huy Cao, Mitchell Rutkowski, Haigou Huang
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Publication number: 20190157140Abstract: An upper layer is formed in a first interlayer dielectric (ILD) layer. The upper layer comprises a plurality of metal interconnects and one or more upper layer air gaps positioned between adjacent metal interconnects. A lower layer is formed in the first ILD layer. The lower layer comprises one or more vias, and one or more lower air gaps positioned between adjacent vias. The upper layer and the lower layer are formed in accordance with a dual-damascene process.Type: ApplicationFiled: January 2, 2019Publication date: May 23, 2019Inventors: Richard A. Conti, Jessica Dechene, Susan S. Fan, Son V. Nguyen, Jeffrey C. Shearer
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Patent number: 10276436Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.Type: GrantFiled: August 5, 2016Date of Patent: April 30, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Benjamin D. Briggs, Jessica Dechene, Elbert E. Huang, Joe Lee, Theodorus E. Standaert
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Patent number: 10269654Abstract: At least one method, apparatus and system disclosed herein involves forming trench silicide region contact. A plurality of fins are formed on a semiconductor substrate. An epitaxial (EPI) feature is formed at a top portion of each fin of the first portion over a first portion of the fins. A gate region is formed over a second portion of the fins. A replacement metal gate (RMG) process is performed in the gate region. A trench is formed in a portion of the gate region. A void is formed adjacent the a portion of the gate region. A first silicon feature is formed in the trench. A second silicon feature is formed in the void. A TS cut region is formed over the trench. The first silicon feature and the second silicon feature are removed. A metallization process is performed in the void to form a contact.Type: GrantFiled: February 6, 2018Date of Patent: April 23, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Jinsheng Gao, Daniel Jaeger, Michael Aquilino, Patrick Carpenter, Jessica Dechene, Huy Cao, Mitchell Rutkowski, Haigou Huang
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Patent number: 10224239Abstract: An upper layer is formed in a first interlayer dielectric (ILD) layer. The upper layer comprises a plurality of metal interconnects and one or more upper layer air gaps positioned between adjacent metal interconnects. A lower layer is formed in the first ILD layer. The lower layer comprises one or more vias, and one or more lower air gaps positioned between adjacent vias. The upper layer and the lower layer are formed in accordance with a dual-damascene process.Type: GrantFiled: August 30, 2017Date of Patent: March 5, 2019Assignee: International Business Machines CorporationInventors: Richard A. Conti, Jessica Dechene, Susan S. Fan, Son V. Nguyen, Jeffrey C. Shearer
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Patent number: 10211138Abstract: A multi-level semiconductor device and a method of fabricating a multi-level semiconductor device involve a first interlayer dielectric (ILD) layer with one or more metal lines formed therein. A silicide is formed on a surface of the first ILD layer and is directly adjacent to each of the one or more metal lines on both sides of each of the one or more metal lines. A second ILD is formed above the silicide, and a via is formed through the second ILD above one of the one or more metal lines. One or more second metal lines are formed above the second ILD, one of which is formed in the via. The second metal line in the via contacts the one of the one or more metal lines and the silicide adjacent to the one of the one or more metal lines.Type: GrantFiled: May 18, 2018Date of Patent: February 19, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Benjamin D. Briggs, Jessica Dechene, Elbert Huang, Joe Lee
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Patent number: 10204797Abstract: The disclosed methods may include depositing an amorphous carbon layer, a SiCN layer, and a TEOS layer; planarizing the semiconductor structure; performing a non-selective etch to remove the SiCN layer, the TEOS layer, and a portion of the amorphous carbon layer; and performing a selective etch of the amorphous carbon layer. The methods may reduce step height differences between first and second regions of the semiconductor structure.Type: GrantFiled: February 6, 2018Date of Patent: February 12, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Jinsheng Gao, Daniel Jaeger, Michael Aquilino, Patrick Carpenter, Junsic Hong, Jessica Dechene, Haigou Huang
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Patent number: 10204827Abstract: An upper layer is formed in a first interlayer dielectric (ILD) layer. The upper layer comprises a plurality of metal interconnects and one or more upper layer air gaps positioned between adjacent metal interconnects. A lower layer is formed in the first ILD layer. The lower layer comprises one or more vias, and one or more lower air gaps positioned between adjacent vias. The upper layer and the lower layer are formed in accordance with a dual-damascene process.Type: GrantFiled: August 30, 2017Date of Patent: February 12, 2019Assignee: International Business Machines CorporationInventors: Richard A. Conti, Jessica Dechene, Susan S. Fan, Son V. Nguyen, Jeffrey C. Shearer
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Publication number: 20180315654Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.Type: ApplicationFiled: June 21, 2018Publication date: November 1, 2018Inventors: Benjamin D. Briggs, Jessica Dechene, Elbert E. Huang, Joe Lee, Theodorus E. Standaert
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Publication number: 20180315653Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.Type: ApplicationFiled: June 21, 2018Publication date: November 1, 2018Inventors: Benjamin D. Briggs, Jessica Dechene, Elbert E. Huang, Joe Lee, Theodorus E. Standaert