Patents by Inventor Jessica M. Torres
Jessica M. Torres has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11869894Abstract: A stacked device structure includes a first device structure including a first body that includes a semiconductor material, and a plurality of terminals coupled with the first body. The stacked device structure further includes an insulator between the first device structure and a second device structure. The second device structure includes a second body such as a fin structure directly above the insulator. The second device structure further includes a gate coupled to the fin structure, a spacer including a dielectric material adjacent to the gate, and an epitaxial structure adjacent to a sidewall of the fin structure and between the spacer and the insulator. A metallization structure is coupled to a sidewall surface of the epitaxial structure, and further coupled with one of the terminals of the first device.Type: GrantFiled: July 13, 2022Date of Patent: January 9, 2024Assignee: Intel CorporationInventors: Aaron D. Lilak, Anh Phan, Patrick Morrow, Willy Rachmady, Gilbert Dewey, Jessica M. Torres, Kimin Jun, Tristan A. Tronic, Christopher J. Jezewski, Hui Jae Yoo, Robert S. Chau, Chi-Hwa Tsang
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Patent number: 11721724Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, wherein the quantum well layer includes an isotopically purified material; a gate dielectric above the quantum well stack; and a gate metal above the gate dielectric, wherein the gate dielectric is between the quantum well layer and the gate metal.Type: GrantFiled: July 1, 2021Date of Patent: August 8, 2023Assignee: Intel CorporationInventors: Nicole K. Thomas, James S. Clarke, Jessica M. Torres, Ravi Pillarisetty, Kanwaljit Singh, Payam Amin, Hubert C. George, Jeanette M. Roberts, Roman Caudillo, David J. Michalak, Zachary R. Yoscovits, Lester Lampert
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Publication number: 20220344376Abstract: A stacked device structure includes a first device structure including a first body that includes a semiconductor material, and a plurality of terminals coupled with the first body. The stacked device structure further includes an insulator between the first device structure and a second device structure. The second device structure includes a second body such as a fin structure directly above the insulator. The second device structure further includes a gate coupled to the fin structure, a spacer including a dielectric material adjacent to the gate, and an epitaxial structure adjacent to a sidewall of the fin structure and between the spacer and the insulator. A metallization structure is coupled to a sidewall surface of the epitaxial structure, and further coupled with one of the terminals of the first device.Type: ApplicationFiled: July 13, 2022Publication date: October 27, 2022Applicant: Intel CorporationInventors: Aaron D. Lilak, Anh Phan, Patrick Morrow, Willy Rachmady, Gilbert Dewey, Jessica M. Torres, Kimin Jun, Tristan A. Tronic, Christopher J. Jezewski, Hui Jae Yoo, Robert S. Chau, Chi-Hwa Tsang
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Patent number: 11430814Abstract: A stacked device structure includes a first device structure including a first body that includes a semiconductor material, and a plurality of terminals coupled with the first body. The stacked device structure further includes an insulator between the first device structure and a second device structure. The second device structure includes a second body such as a fin structure directly above the insulator. The second device structure further includes a gate coupled to the fin structure, a spacer including a dielectric material adjacent to the gate, and an epitaxial structure adjacent to a sidewall of the fin structure and between the spacer and the insulator. A metallization structure is coupled to a sidewall surface of the epitaxial structure, and further coupled with one of the terminals of the first device.Type: GrantFiled: March 5, 2018Date of Patent: August 30, 2022Assignee: Intel CorporationInventors: Aaron D. Lilak, Anh Phan, Patrick Morrow, Willy Rachmady, Gilbert Dewey, Jessica M. Torres, Kimin Jun, Tristan A. Tronic, Christopher J. Jezewski, Hui Jae Yoo, Robert S. Chau, Chi-Hwa Tsang
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Patent number: 11406972Abstract: Catalysts for facilitating cross-linking of liquid precursors into solid dielectric materials are disclosed. Initially, catalysts are protected, either by coordination with other compounds or by conversion to an ionic salt. Protection prevents catalysts from facilitating cross-linking unless activated. A catalyst is activated upon receiving an excitation, e.g. thermal excitation by heating. Upon receiving an excitation, protection of a catalyst dissociates, decomposes, becomes neutralized, or is otherwise transformed to allow the catalyst to facilitate cross-linking of the precursors into solid dielectric materials. Methods for fabricating dielectric materials using such protected catalysts as well as devices comprising the resulting materials are also described. Dielectric materials comprising cross-linked cyclic carbosilane units having a ring structure including C and Si may be formed in this manner.Type: GrantFiled: December 4, 2015Date of Patent: August 9, 2022Assignee: Intel CorporationInventors: James M. Blackwell, David J. Michalak, Jessica M. Torres, Marie Krysak, Jeffery D. Bielefeld
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Publication number: 20210328019Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, wherein the quantum well layer includes an isotopically purified material; a gate dielectric above the quantum well stack; and a gate metal above the gate dielectric, wherein the gate dielectric is between the quantum well layer and the gate metal.Type: ApplicationFiled: July 1, 2021Publication date: October 21, 2021Applicant: Intel CorporationInventors: Nicole K. Thomas, James S. Clarke, Jessica M. Torres, Ravi Pillarisetty, Kanwaljit Singh, Payam Amin, Hubert C. George, Jeanette M. Roberts, Roman Caudillo, David J. Michalak, Zachary R. Yoscovits, Lester Lampert
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Patent number: 11152254Abstract: An integrated circuit die, a semiconductor structure, and a method of fabricating the semiconductor structure are disclosed. The integrated circuit die includes a substrate and a first anchor and a second anchor disposed on the substrate in a first plane. The integrated circuit die also includes a first wire disposed on the first anchor in the first plane, a third wire disposed on the second anchor in the first plane, and a second wire and a fourth wire suspended above the substrate in the first plane. The second wire is disposed between the first wire and the third wire and the third wire is disposed between the second wire and the fourth wire. The integrated circuit die further includes a dielectric material disposed between upper portions of the first wire, the second wire, the third wire, and the fourth wire to encapsulate an air gap.Type: GrantFiled: December 28, 2016Date of Patent: October 19, 2021Assignee: Intel CorporationInventors: Manish Chandhok, Sudipto Naskar, Stephanie A. Bojarski, Kevin Lin, Marie Krysak, Tristan A. Tronic, Hui Jae Yoo, Jeffery D. Bielefeld, Jessica M. Torres
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Patent number: 11114530Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, wherein the quantum well layer includes an isotopically purified material; a gate dielectric above the quantum well stack; and a gate metal above the gate dielectric, wherein the gate dielectric is between the quantum well layer and the gate metal.Type: GrantFiled: December 17, 2017Date of Patent: September 7, 2021Assignee: Intel CorporationInventors: Nicole K. Thomas, James S. Clarke, Jessica M. Torres, Ravi Pillarisetty, Kanwaljit Singh, Payam Amin, Hubert C. George, Jeanette M. Roberts, Roman Caudillo, David J. Michalak, Zachary R. Yoscovits, Lester Lampert
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Patent number: 11024538Abstract: In an example, there is disclosed an integrated circuit, having: a first layer having a dielectric, a first conductive interconnect and a second conductive interconnect; a second layer having a third conductive interconnect; a conductive via between the first layer and the second layer to electrically couple the second conductive interconnect to the third conductive interconnect; and an etch-resistant plug disposed vertically between the first layer and second layer and disposed to prevent the via from electrically shorting to the first conductive interconnect.Type: GrantFiled: December 31, 2016Date of Patent: June 1, 2021Assignee: Intel CorporationInventors: Kevin L. Lin, Tayseer Mahdi, Jessica M. Torres, Jeffery D. Bielefeld, Marie Krysak, James M. Blackwell
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Publication number: 20210036110Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, wherein the quantum well layer includes an isotopically purified material; a gate dielectric above the quantum well stack; and a gate metal above the gate dielectric, wherein the gate dielectric is between the quantum well layer and the gate metal.Type: ApplicationFiled: December 17, 2017Publication date: February 4, 2021Applicant: Intel CorporationInventors: Nicole K. Thomas, James S. Clarke, Jessica M. Torres, Ravi Pillarisetty, Kanwaljit Singh, Payam Amin, Hubert C. George, Jeanette M. Roberts, Roman Caudillo, David J. Michalak, Zachary R. Yoscovits, Lester Lampert
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Publication number: 20200395386Abstract: A stacked device structure includes a first device structure including a first body that includes a semiconductor material, and a plurality of terminals coupled with the first body. The stacked device structure further includes an insulator between the first device structure and a second device structure. The second device structure includes a second body such as a fin structure directly above the insulator. The second device structure further includes a gate coupled to the fin structure, a spacer including a dielectric material adjacent to the gate, and an epitaxial structure adjacent to a sidewall of the fin structure and between the spacer and the insulator. A metallization structure is coupled to a sidewall surface of the epitaxial structure, and further coupled with one of the terminals of the first device.Type: ApplicationFiled: March 5, 2018Publication date: December 17, 2020Applicant: Intel CorporationInventors: Aaron D. Lilak, Anh Phan, Patrick Morrow, Willy Rachmady, Gilbert Dewey, Jessica M. Torres, Kimin Jun, Tristan A. Tronic, Christopher J. Jezewski, Hui Jae Yoo, Robert S. Chau, Chi-Hwa Tsang
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Patent number: 10763347Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum processing device may include: a quantum well stack having alternatingly arranged relaxed and strained layers; and a plurality of gates disposed above the quantum well stack to control quantum dot formation in the quantum well stack.Type: GrantFiled: December 14, 2016Date of Patent: September 1, 2020Assignee: Intel CorporationInventors: Payam Amin, Nicole K. Thomas, James S. Clarke, Jessica M. Torres, Ravi Pillarisetty, Hubert C. George, Kanwaljit Singh, Van H. Le, Jeanette M. Roberts, Roman Caudillo, Zachary R. Yoscovits, David J. Michalak
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Publication number: 20200098629Abstract: In an example, there is disclosed an integrated circuit, having: a first layer having a dielectric, a first conductive interconnect and a second conductive interconnect; a second layer having a third conductive interconnect; a conductive via between the first layer and the second layer to electrically couple the second conductive interconnect to the third conductive interconnect; and an etch-resistant plug disposed vertically between the first layer and second layer and disposed to prevent the via from electrically shorting to the first conductive interconnect.Type: ApplicationFiled: December 31, 2016Publication date: March 26, 2020Applicant: Intel CorporationInventors: Kevin L. Lin, Tayseer Mahdi, Jessica M. Torres, Jeffery D. Bielefeld, Marie Krysak, James M. Blackwell
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Patent number: 10529660Abstract: Pore-filled dielectric materials for semiconductor structure fabrication, and methods of fabricating pore-filled dielectric materials for semiconductor structure fabrication, are described. In an example, a method of fabricating a pore-filled dielectric material for semiconductor structure fabrication includes forming a trench in a material layer. The method also includes filling the trench with a porous dielectric material using a spin-on deposition process. The method also includes filling pores of the porous dielectric material with a metal-containing material using an atomic layer deposition (ALD) process.Type: GrantFiled: September 30, 2016Date of Patent: January 7, 2020Assignee: Intel CorporationInventors: Jessica M. Torres, Jeffery D. Bielefeld, Mauro J. Kobrinsky, Christopher J. Jezewski, Gopinath Bhimarasetti
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Publication number: 20190385897Abstract: An integrated circuit die, a semiconductor structure, and a method of fabricating the semiconductor structure are disclosed. The integrated circuit die includes a substrate and a first anchor and a second anchor disposed on the substrate in a first plane. The integrated circuit die also includes a first wire disposed on the first anchor in the first plane, a third wire disposed on the second anchor in the first plane, and a second wire and a fourth wire suspended above the substrate in the first plane. The second wire is disposed between the first wire and the third wire and the third wire is disposed between the second wire and the fourth wire. The integrated circuit die further includes a dielectric material disposed between upper portions of the first wire, the second wire, the third wire, and the fourth wire to encapsulate an air gap.Type: ApplicationFiled: December 28, 2016Publication date: December 19, 2019Inventors: Manish CHANDHOK, Sudipto NASKAR, Stephanie A. BOJARSKI, Kevin LIN, Marie KRYSAK, Tristan A. TRONIC, Hui Jae YOO, Jeffery D. BIELEFELD, Jessica M. TORRES
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Publication number: 20190334020Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum processing device may include: a quantum well stack having alternatingly arranged relaxed and strained layers; and a plurality of gates disposed above the quantum well stack to control quantum dot formation in the quantum well stack.Type: ApplicationFiled: December 14, 2016Publication date: October 31, 2019Applicant: Intel CorporationInventors: Payam Amin, Nicole K. Thomas, James S. Clarke, Jessica M. Torres, Ravi Pillarisetty, Hubert C. George, Kanwaljit Singh, Van H. Le, Jeanette M. Roberts, Roman Caudillo, Zachary R. Yoscovits, David J. Michalak
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Patent number: 10388848Abstract: Embodiments of the present disclosure describe use of isotopically purified materials in donor- or acceptor-based spin qubit devices and assemblies. An exemplary spin qubit device assembly may include a semiconductor host layer that includes an isotopically purified material, a dopant atom in the semiconductor host layer, and a gate proximate to the dopant atom. An isotopically purified material may include a lower atomic-percent of isotopes with nonzero nuclear spin than the natural abundance of those isotopies in the non-isotopically purified material. Reducing the presence of isotopes with nonzero nuclear spin in a semiconductor host layer may improve qubit coherence and thus performance of spin qubit devices and assemblies.Type: GrantFiled: March 19, 2018Date of Patent: August 20, 2019Assignee: Intel CorporationInventors: Nicole K. Thomas, James S. Clarke, Jessica M. Torres, Lester Lampert, Ravi Pillarisetty, Hubert C. George, Kanwaljit Singh, Jeanette M. Roberts, Roman Caudillo, Zachary R. Yoscovits, David J. Michalak
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Publication number: 20190252313Abstract: Pore-filled dielectric materials for semiconductor structure fabrication, and methods of fabricating pore-filled dielectric materials for semiconductor structure fabrication, are described. In an example, a method of fabricating a pore-filled dielectric material for semiconductor structure fabrication includes forming a trench in a material layer. The method also includes filling the trench with a porous dielectric material using a spin-on deposition process. The method also includes filling pores of the porous dielectric material with a metal-containing material using an atomic layer deposition (ALD) process.Type: ApplicationFiled: September 30, 2016Publication date: August 15, 2019Inventors: Jessica M. TORRES, Jeffery D. BIELEFELD, Mauro J. KOBRINSKY, Christopher J. JEZEWSKI, Gopinath BHIMARASETTI
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Publication number: 20190044045Abstract: Embodiments of the present disclosure describe use of isotopically purified materials in donor- or acceptor-based spin qubit devices and assemblies. An exemplary spin qubit device assembly may include a semiconductor host layer that includes an isotopically purified material, a dopant atom in the semiconductor host layer, and a gate proximate to the dopant atom. An isotopically purified material may include a lower atomic-percent of isotopes with nonzero nuclear spin than the natural abundance of those isotopies in the non-isotopically purified material. Reducing the presence of isotopes with nonzero nuclear spin in a semiconductor host layer may improve qubit coherence and thus performance of spin qubit devices and assemblies.Type: ApplicationFiled: March 19, 2018Publication date: February 7, 2019Applicant: Intel CorporationInventors: Nicole K. Thomas, James S. Clarke, Jessica M. Torres, Lester Lampert, Ravi Pillarisetty, Hubert C. George, Kanwaljit Singh, Jeanette M. Roberts, Roman Caudillo, Zachary R. Yoscovits, David J. Michalak
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Publication number: 20180236440Abstract: Catalysts for facilitating cross-linking of liquid precursors into solid dielectric materials are disclosed. Initially, catalysts are protected, either by coordination with other compounds or by conversion to an ionic salt. Protection prevents catalysts from facilitating cross-linking unless activated. A catalyst is activated upon receiving an excitation, e.g. thermal excitation by heating. Upon receiving an excitation, protection of a catalyst dissociates, decomposes, becomes neutralized, or is otherwise transformed to allow the catalyst to facilitate cross-linking of the precursors into solid dielectric materials. Methods for fabricating dielectric materials using such protected catalysts as well as devices comprising the resulting materials are also described. Dielectric materials comprising cross-linked cyclic carbosilane units having a ring structure including C and Si may be formed in this manner.Type: ApplicationFiled: December 4, 2015Publication date: August 23, 2018Applicant: Intel CorporationInventors: James M. BLACKWELL, David J. Michalak, Jessica M. Torres, Marie KRYSAK, Jeffery D. Bielefeld