Patents by Inventor JESSIE LIN

JESSIE LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11342179
    Abstract: A semiconductor structure having a Si substrate heterointegrated with GaN and a method for fabricating the same is disclosed. The method uses a (100) silicon substrate to fabricate a hundred nanometer scale hole and uses wet etching to etch the silicon substrate, thereby exposing the (111) crystal surface of the silicon substrate. The (111) crystal surface is used as a nucleating crystal surface of an AlN buffer layer and GaN. When GaN is grown, silane is reacted with GaN to adjust the concentration of doping silicon atoms into GaN, thereby forming a semiconductor structure having a Si substrate heterointegrated with GaN.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: May 24, 2022
    Assignee: National Chiao Tung University
    Inventors: Edward Yi Chang, Chieh-Hsi Chuang, Jessie Lin
  • Patent number: 11297353
    Abstract: A method of measuring a banding artefact in an image includes generating a gradient profile from the image, where the gradient profile includes respective gradient magnitudes of pixels of the image; generating, using the gradient profile, a candidate banding pixel (CBP) map, where each location of the CBP map is such that a gradient magnitude of the gradient profile of a corresponding pixel of the image being greater than a first threshold and smaller than a second threshold; generating, using the CBP map, a banding edge map (BEM), where the BEM includes connected banding edges of the image; generating, using the BEM, a banding visibility map (BVM), where the BVM includes a respective banding metric for at least some pixels of the image; and generating a banding index of the image using the BVM.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: April 5, 2022
    Assignee: GOOGLE LLC
    Inventors: Jessie Lin, Zhengzhong Tu
  • Patent number: 11271109
    Abstract: A silicon metal-oxide-semiconductor field effect transistor with a wide-bandgap III-V compound semiconductor drain and a method for fabricating the same are disclosed. The method fabricates a hundred nanometer-scale hole in a (100) silicon substrate to expose the (111) facet of the silicon substrate, which favors to use selective area growth to form lattice matched III-V materials with high quality.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: March 8, 2022
    Assignee: National Chiao Tung University
    Inventors: Edward Yi Chang, Mau-Chung Frank Chang, Chieh-Hsi Chuang, Jessie Lin
  • Publication number: 20210321142
    Abstract: A method of measuring a banding artefact in an image includes generating a gradient profile from the image, where the gradient profile includes respective gradient magnitudes of pixels of the image; generating, using the gradient profile, a candidate banding pixel (CBP) map, where each location of the CBP map is such that a gradient magnitude of the gradient profile of a corresponding pixel of the image being greater than a first threshold and smaller than a second threshold; generating, using the CBP map, a banding edge map (BEM), where the BEM includes connected banding edges of the image; generating, using the BEM, a banding visibility map (BVM), where the BVM includes a respective banding metric for at least some pixels of the image; and generating a banding index of the image using the BVM.
    Type: Application
    Filed: April 6, 2020
    Publication date: October 14, 2021
    Inventors: Jessie Lin, Zhengzhong Tu
  • Publication number: 20210159338
    Abstract: A silicon metal-oxide-semiconductor field effect transistor with a wide-bandgap III-V compound semiconductor drain and a method for fabricating the same are disclosed. The method fabricates a hundred nanometer-scale hole in a (100) silicon substrate to expose the (111) facet of the silicon substrate, which favors to use selective area growth to form lattice matched III-V materials with high quality.
    Type: Application
    Filed: August 31, 2020
    Publication date: May 27, 2021
    Inventors: EDWARD YI CHANG, MAU-CHUNG FRANK CHANG, CHIEH-HSI CHUANG, JESSIE LIN
  • Publication number: 20210118670
    Abstract: A semiconductor structure having a Si substrate heterointegrated with GaN and a method for fabricating the same is disclosed. The method uses a (100) silicon substrate to fabricate a hundred nanometer scale hole and uses wet etching to etch the silicon substrate, thereby exposing the (111) crystal surface of the silicon substrate. The (111) crystal surface is used as a nucleating crystal surface of an AlN buffer layer and GaN. When GaN is grown, silane is reacted with GaN to adjust the concentration of doping silicon atoms into GaN, thereby forming a semiconductor structure having a Si substrate heterointegrated with GaN.
    Type: Application
    Filed: December 9, 2020
    Publication date: April 22, 2021
    Inventors: EDWARD YI CHANG, CHIEH-HSI CHUANG, JESSIE LIN
  • Publication number: 20200373153
    Abstract: A semiconductor structure having a Si substrate heterointegrated with GaN and a method for fabricating the same is disclosed. The method uses a (100) silicon substrate to fabricate a hundred nanometer scale hole and uses wet etching to etch the silicon substrate, thereby exposing the (111) crystal surface of the silicon substrate. The (111) crystal surface is used as a nucleating crystal surface of an AlN buffer layer and GaN. When GaN is grown, silane is reacted with GaN to adjust the concentration of doping silicon atoms into GaN, thereby forming a semiconductor structure having a Si substrate heterointegrated with GaN.
    Type: Application
    Filed: July 23, 2019
    Publication date: November 26, 2020
    Inventors: EDWARD YI CHANG, CHIEH-HSI CHUANG, JESSIE LIN