Patents by Inventor Jesus S. Pena-Finol

Jesus S. Pena-Finol has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5832370
    Abstract: A transmitter (300) sends a transmitted current (I.sub.203, I.sub.204) along a transmit signal path (203, 204) to a receiver (400) having a low input impedance. The receiver includes a transistor structure (402, 404) that amplifies the transmitted current and feeds it back to the input of the receiver to maintain the low input impedance and a substantially constant voltage on the transmit signal path. The substantially constant voltage at the input of the receiver avoids interference with other circuits (206, 208) located along the transmit signal path.
    Type: Grant
    Filed: September 26, 1996
    Date of Patent: November 3, 1998
    Assignee: Motorola, Inc.
    Inventors: Jesus S. Pena-Finol, Mark J. Chambers, Erica G. Miller, Philippe Gorisse
  • Patent number: 5617056
    Abstract: A base current compensation circuit (10) generates a current that tracks a gain of a transistor (11). The compensation circuit (10) includes a current mirror formed by a mirror transistor (12) and an output transistor (14). The mirror transistor (12) is connected to the transistor (11) whose gain is tracked. A current source (16) and a feedback transistor (13) causes the mirror transistor (12) to draw a base current from the transistor (11) so that a collector current of the transistor (11) matches a reference current. The output transistor (14) amplifies the base current of the transistor (11) to generate the tracking current in the collector electrode of the output transistor (14).
    Type: Grant
    Filed: July 5, 1995
    Date of Patent: April 1, 1997
    Assignee: Motorola, Inc.
    Inventors: William E. Main, David K. Lovelace, Jesus S. Pena-Finol
  • Patent number: 5465409
    Abstract: A radio having two architectural platforms integrated in one integrated circuit (IC). A synthesizer controller (312) selects between an offset local oscillator (LO) synthesizer (318) and a second LO synthesizer (316) to provide a common architecture for either an Frequency Division Duplex (FDD) or Time Division Duplex (TDD) system design while providing isolation between the two frequency sources. An offset LO signal (319) is translated to an isolated LO signal 310 and combined with a main LO signal (322) to provide the FDD platform. A second LO signal (314) is translated into the isolated LO signal 310 and combined with the main LO signal (322) to provide the TDD platform. The second LO synthesizer signal (314) is common to both systems in the receive mode.
    Type: Grant
    Filed: March 7, 1994
    Date of Patent: November 7, 1995
    Assignee: Motorola, Inc.
    Inventors: Jaime A. Borras, Mark J. Chambers, Jesus S. Pena Finol, Armando J. Gonzalez, Cesar W. Carralero, Sayed H. Beladi, Levent Y. Erbora
  • Patent number: 5381114
    Abstract: A continuous time common mode feedback amplifier CTCMFB (300) is suitable for applications requiring fully differential amplifiers in low voltage supply requirements. Two mirror image, low gain CMOS amplifiers (MP0/MP2 and MP3/MP4) in the CTCMFB (300) define and stabilize the common mode output voltage, Vcm, of the main differential amplifier (102). The transient response of the common mode amplifier (300) can be adjusted independently of the transient response of the main differential amplifier (102), allowing fast transient response to the main differential amplifier.
    Type: Grant
    Filed: April 4, 1994
    Date of Patent: January 10, 1995
    Assignee: Motorola, Inc.
    Inventors: Jesus S. Pena-Finol, Mark J. Chambers, James B. Phillips
  • Patent number: 4546275
    Abstract: A four-quadrant NMOS transconductance multiplier including plural NMOS transistors formed in a substrate to produce a pair of summer stages and a pair of squaring stages which process a pair of input signals V.sub.1, V.sub.2 to produce an output signal V.sub.o according to the quarter-square algebraic identity,V.sub.o =1/4[(V.sub.1 +V.sub.2).sup.2 -(V.sub.1 -V.sub.2).sup.2 ]=V.sub.1 V.sub.2.In a preferred embodiment, the substrate doping N.sub.A =6.7.times.10.sup.15 cm.sup.-3 and the channel width and channel length of each of the NMOS transistors forming the summer and squaring stages is greater than 10 .mu.m.
    Type: Grant
    Filed: June 2, 1983
    Date of Patent: October 8, 1985
    Assignee: Georgia Tech Research Institute
    Inventors: Jesus S. Pena-Finol, Joseph A. Connelly