Abstract: The present invention relates to an apparatus and method for controlling a bit line sense amplifier, comprising a first inverter for inverting data of a first bit line; a second inverter for inverting data of a second bit line; a first and a second switch responsive to an output signal from a column decoder for switching between an output terminal of the first and the second inverter and a data bus, respectively; a third and a fourth switch responsive to an offset compensation signal for switching between an input terminal and an output terminal of the first inverter and the second inverter, respectively; and an offset compensation signal generator for generating an offset compensation signal in accordance with a row control signal.

Abstract: A sense amplifier comprising a data refresh amplifier for supplying voltages to true and complementary bit lines in response to a first control signal to amplify true and complementary data on the true and complementary bit lines, respectively, a first transistor for amplifying current of the true data on the true bit line in response to a second control signal and transferring the amplified true data to a true input/output line, a second transistor for amplifying current of the complementary data on the complementary bit line in response to the second control signal and transferring the amplified complementary data to a complementary input/output line, a first switch for selectively forming a current path between the true input/output line and the true bit line, and a second switch for selectively forming a current path between the complementary input/output line and the complementary bit line.

Abstract: A method for forming a transistor comprising the steps of: forming a trench in a substrate; filling an insulating layer in the lower portion of said trench except for the upper portion thereof; filling a conductive layer in the upper portion of said trench and on said insulating layer for a channel of the said transistor; forming a gate oxide layer on the resulting structure; and forming a gate electrode on said gate oxide layer; and implanting impurity ions into said substrate to form a source/drain region.

Abstract: A reference voltage generation circuit for a semiconductor memory device comprising a reference voltage generator for generating first and second reference voltages, the first and second reference voltages having the opposite response characteristics with respect to a variation in a temperature or a supply voltage, a start-up circuit for determining an initial condition of the reference voltage generator in response to the supply voltage to stabilize the operation of the reference voltage generator, and a voltage amplifier for compensating a target reference voltage for the temperature variation in response to the first and second reference voltages from the reference voltage generator so that the target reference voltage can always be constant in level. The first reference voltage has a positive response characteristic with respect to the temperature and the supply voltage and the second reference voltage has a negative response characteristic with respect to the temperature and the supply voltage.

Abstract: A sense amplifier comprising a data refresh amplifier for supplying voltages to true and complementary bit lines in response to a first control signal to amplify true and complementary data on the true and complementary bit lines, respectively, a first transistor fox amplifying current of the true data on the true bit line in response to a second control signal and transferring the amplified true data to a true input/output line, a second transistor for amplifying current of the complementary data on the complementary bit line in response to the second control signal and transferring the amplified complementary data to a complementary input/output line, a first switch for selectively forming a current path between the true input/output line and the true bit line, and a second switch for selectively forming a current path between the complementary input/output line and the complementary bit line.