Abstract: A current-mode sensing structure used in a high-density multiple-port register in logic processing and a method for the same are proposed. First, a reference current is defined by a dummy word line of a dummy cell and output. A multiple-port register file cell is then used to send out a select signal of “0” or “1” and output a cell current according to the select signal and the reference current. Finally, the cell current and the reference current are sent to a current comparator amplifier, which senses and outputs a difference value between the cell current and the reference current to perform session at once (SAO) recording. Because the difference value has only two possibilities: the reference current or its negative, the sensing time of the current comparator amplifier can be shortened.

Abstract: A current-mode sensing structure used in a high-density multiple-port register in logic processing and a method for the same are proposed. First, a reference current is defined by a dummy word line of a dummy cell and output. A multiple-port register file cell is then used to send out a select signal of “0” or “1” and output a cell current according to the select signal and the reference current. Finally, the cell current and the reference current are sent to a current comparator amplifier, which senses and outputs a difference value between the cell current and the reference current to perform session at once (SAO) recording. Because the difference value has only two possibilities: the reference current or its negative, the sensing time of the current comparator amplifier can be shortened.

Abstract: A current-mode sensing structure of a high-density multiple-port register in embedded flash memory procedure and a method for the same are proposed. A multiple-port register file cell is used to send out a select signal of “0” or “1”. Based on this select signal, a turn-on voltage and a cell current are output. Next, a dummy bit line of an embedded dummy flash cell is used to define a reference voltage according to the turn-on voltage and generate a corresponding reference current. Finally, the cell current and the reference current are sent to a current comparator amplifier, which senses and outputs a difference value between the cell current and the reference current to perform session at once (SAO) recording. Because the difference value has only two possibilities: the reference current or its negative, the sensing time of the current comparator amplifier can be shortened.

Abstract: The present invention discloses a multiple-stage FIFO mechanism capable of receiving data signals correctly. The circuit includes a write-enable pulse sequencer for sequentially generating a plurality of write-enable signals. An N-stage FIFO sequentially stores an input data and outputs the input data. An output stage selector sequentially generates a control signal. And a multiplexer selectively outputs the input data from the N-stage FIFO.

Abstract: A structure to inspect high/low of memory cell threshold voltage using a current mode sense amplifier. A current mode sense amplifier is used to compare a memory cell current of a selected memory cell and a reference current to determine high/low of the threshold voltage. Since the current input is compared, it is not necessary to provide a reference word line and a reference memory cell circuit. The area is thus decreased, and the waiting time to convert current to voltage is saved to greatly increase the access speed.

Abstract: The present invention discloses a multiple-stage FIFO mechanism capable of receiving data signals correctly. The circuit includes a write-enable pulse sequencer for sequentially generating a plurality of write-enable signals. An N-stage FIFO sequentially stores an input data and outputs the input data. An output stage selector sequentially generates a control signal. And a multiplexer selectively outputs the input data from the N-stage FIFO.

Abstract: A voltage stabilizer of an embedded flash memory to modulate an input voltage VDD with a wide range of variation to a fixed voltage as an output. The voltage at the bit line of the selected memory cell can be fixed to avoid error access. The voltage stablizer of the embedded flash memory performs a voltage range inspection using a voltage inspector. Comparing to a standard value, an input voltage higher or lower than the standard value is output from a first terminal or a second terminal, respectively. The input voltage output from the first or second terminals is then stabilized to output a fixed voltage.

Abstract: A fixed frequency clock generator generates and outputs a fixed frequency clock by using a number of fixed delay units and a number of inverters that both are connected in series alternately and evenly. More particularly, the fixed delay unit involves two fixed current sources and two controlling switchers, plus an inverter that controls a charging and a discharging of a capacitor. Then the electric potential of the capacitor and a stable voltage source respectively send the current to the comparator. The time of charging and discharging of the capacitor is fixed, therefore the time of the electric potential of the capacitor is fixed for reach to the fixed voltage source, and the sequence of the output signal of the comparator is also fixed. In the above description, the fixed delay unit generates the fixed frequency.

Abstract: A structure to inspect high/low of memory cell threshold voltage using a current mode sense amplifier. A current mode sense amplifier is used to compare a memory cell current of a selected memory cell and a reference current to determine high/low of the threshold voltage. Since the current input is compared, it is not necessary to provide a reference word line and a reference memory cell circuit. The area is thus decreased, and the waiting time to convert current to voltage is saved to greatly increase the access speed.

Abstract: A voltage stabilizer of an embedded flash memory to modulate an input voltage VDD with a wide range of variation to a fixed voltage as an output. The voltage at the bit line of the selected memory cell can be fixed to avoid error access. The voltage stabilizer of the embedded flash memory performs a voltage range inspection using a voltage inspector. Comparing to a standard value, an input voltage higher or lower than the standard value is output from a first terminal or a second terminal, respectively. The input voltage output from the first or second terminals is then stabilized to output a fixed voltage.

Abstract: A fixed frequency clock generator generates and outputs a fixed frequency clock by using a number of fixed delay units and a number of inverters that both are connected in series alternately and evenly. More particularly, the fixed delay unit involves two fixed current sources and two controlling switchers, plus an inverter that controls a charging and a discharging of a capacitor. Then the electric potential of the capacitor and a stable voltage source respectively send the current to the comparator. The time of charging and discharging of the capacitor is fixed, therefore the time of the electric potential of the capacitor is fixed for reach to the fixed voltage source, and the sequence of the output signal of the comparator is also fixed. In the above description, the fixed delay unit generates the fixed frequency.

Abstract: This present invention discloses a circuit for generating a delay signal, which includes a first delay line for generating a first delay signal, a second delay line for generating a second delay signal, a delay unit for generating an internal delay signal, a first phase detector for generating a first control signal, a second phase detector for generating a second control signal. There's a delay line monitor for generating the first delay control signal and the second delay control signal, and a DTC delay unit for generating the delay signal.