Patents by Inventor Jeyanandh K. Paramesh

Jeyanandh K. Paramesh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • On-die coupled inductor structures for improving quality factor
    Patent number: 7456720
    Abstract: On-die coupled inductor structures are disclosed that are capable of reducing the occurrence of charge crowding within the structure.
    Type: Grant
    Filed: May 17, 2005
    Date of Patent: November 25, 2008
    Assignee: Intel Corporation
    Inventors: Mostafa Elmala, Jeyanandh K Paramesh
  • Integrated parallel power amplifier
    Patent number: 7414478
    Abstract: A parallel power amplifier includes a carrier amplifier and peak amplifier coupled to receive signals from a quadrature hybrid made up of slab inductors in an integrated circuit. The slab inductors may be on different layers in the integrated circuit and may have similar or dissimilar shapes.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: August 19, 2008
    Assignee: Intel Corporation
    Inventors: Mostafa Elmala, Jeyanandh K Paramesh
  • Transceiver with calibrated I and Q paths and methods for deconvolved calibration
    Patent number: 7333423
    Abstract: Phase and amplitude offsets of a multicarrier transceiver may be reduced by measuring receiver amplitude and phase mismatches of receiver radio-frequency (RF) circuitry by performing a fast Fourier transform (FFT) on a receiver calibration signal.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: February 19, 2008
    Assignee: Intel Corporation
    Inventors: Georgios Palaskas, Ashoke Ravi, Jeyanandh K. Paramesh, Richard B. Nicholls, Krishnamurthy Soumyanath