Patents by Inventor Jeyenth Vijayaraghavan

Jeyenth Vijayaraghavan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and circuitry to translate a differential logic signal to a CMOS logic signal
    Patent number: 7777521
    Abstract: Disclosed are various embodiments of a differential logic to CMOS logic translator including a level-shifting and buffering stage configured to receive differential inputs and to provide resulting signals with lower common mode voltage. Further, a gain stage is included to receive the resulting signals and to provide increased swing signals. A CMOS buffer is also included and is configured to receive the increased swing signals and to provide a CMOS logic output. Also disclosed is a method of translating a differential logic signal to a CMOS logic signal including level-shifting and buffering differential input signals to provide resulting signals with lower common mode voltage. The method also includes using a gain stage to provide increased swing signals from the resulting lower common mode signals and using a CMOS buffer to provide a CMOS output from the increased swing signals.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: August 17, 2010
    Assignee: Cypress Semiconductor Corporation
    Inventors: Sherif Hanna, Greg J. Landry, Alan ReFalo, Jeyenth Vijayaraghavan
  • High-speed differential logic to CMOS translator architecture with low data-dependent jitter and duty cycle distortion
    Publication number: 20080143385
    Abstract: Disclosed are various embodiments of a differential logic to CMOS logic translator including a level-shifting and buffering stage configured to receive differential inputs and to provide resulting signals with lower common mode voltage. Further, a gain stage is included to receive the resulting signals and to provide increased swing signals. A CMOS buffer is also included and is configured to receive the increased swing signals and to provide a CMOS logic output. Also disclosed is a method of translating a differential logic signal to a CMOS logic signal including level-shifting and buffering differential input signals to provide resulting signals with lower common mode voltage. The method also includes using a gain stage to provide increased swing signals from the resulting lower common mode signals and using a CMOS buffer to provide a CMOS output from the increased swing signals.
    Type: Application
    Filed: November 27, 2007
    Publication date: June 19, 2008
    Inventors: Sherif Hanna, Greg J. Landry, Alan ReFalo, Jeyenth Vijayaraghavan
  • High-speed differential logic to CMOS translator architecture with low data-dependent jitter and duty cycle distortion
    Patent number: 7301370
    Abstract: Disclosed are various embodiments of a differential logic to CMOS logic translator including a level-shifting and buffering stage configured to receive differential inputs and to provide resulting signals with lower common mode voltage. Further, a gain stage is included to receive the resulting signals and to provide increased swing signals. A CMOS buffer is also included and is configured to receive the increased swing signals and to provide a CMOS logic output. Also disclosed is a method of translating a differential logic signal to a CMOS logic signal including level-shifting and buffering differential input signals to provide resulting signals with lower common mode voltage. The method also includes using a gain stage to provide increased swing signals from the resulting lower common mode signals and using a CMOS buffer to provide a CMOS output from the increased swing signals.
    Type: Grant
    Filed: May 24, 2004
    Date of Patent: November 27, 2007
    Assignee: Cypress Semiconductor Corporation
    Inventors: Sherif Hanna, Greg J. Landry, Alan ReFalo, Jeyenth Vijayaraghavan