Patents by Inventor Jhalak Gupta

Jhalak Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240184781
    Abstract: Systems, devices, computer-implemented methods, and tangible non-transitory computer-readable media for generating reports from one or more databases that store disparate datasets are provided. Specifically, the proposed systems enable the intelligent generation of reports from multiple datasets by automatically determining a proposed set of join configurations for combination of the multiple datasets. The proposed set of join configurations can be executed as proposed and/or can be edited or customized by the user to generate reports from the multiple datasets. Thus, the proposed systems and methods can provide intuitive and user-friendly tools for generating data reports that accurately synthesize and summarize data contained in multiple different datasets.
    Type: Application
    Filed: December 2, 2022
    Publication date: June 6, 2024
    Inventors: Parker Rouse Conrad, Kyle Michael Boston, Nikunj Aggarwal, Siddhartha Gunda, Chewei Hu, Himanshu Nanda, VenuMadhav Kattagoni, Jhalak Gupta, Utkarsh Bhatia, Sanket Ketkar
  • Patent number: 10839877
    Abstract: A protection module for an electronic circuit prevents unintended write operations by a master module to functional registers of a protected module. The protection module includes soft lock bits (SLBs) that indicate whether corresponding functional registers are locked and control logic that supports (i) a page select (PS) control parameter that indicates whether access by the master module is to the functional registers or the SLBs and (ii) a mode select (MS) control parameter that indicates whether access by the master module to the functional registers is in a normal access mode, in which each written-to functional register is left unlocked, or an auto-lock access mode, in which each just-written-to functional register is automatically locked by setting the corresponding SLB. The functional registers and the SLBs share addresses that can fit within a single address space that includes the control parameters.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: November 17, 2020
    Assignee: NXP USA, INC.
    Inventors: Arun Kumar Barman, Parul Bansal, Jhalak Gupta
  • Publication number: 20200342924
    Abstract: A protection module for an electronic circuit prevents unintended write operations by a master module to functional registers of a protected module. The protection module includes soft lock bits (SLBs) that indicate whether corresponding functional registers are locked and control logic that supports (i) a page select (PS) control parameter that indicates whether access by the master module is to the functional registers or the SLBs and (ii) a mode select (MS) control parameter that indicates whether access by the master module to the functional registers is in a normal access mode, in which each written-to functional register is left unlocked, or an auto-lock access mode, in which each just-written-to functional register is automatically locked by setting the corresponding SLB. The functional registers and the SLBs share addresses that can fit within a single address space that includes the control parameters.
    Type: Application
    Filed: April 23, 2019
    Publication date: October 29, 2020
    Inventors: Arun Kumar Barman, Parul Bansal, Jhalak Gupta