Patents by Inventor Jhang W. Lee

Jhang W. Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Heteroepitaxy by growth of thermally strained homojunction superlattice buffer layers
    Patent number: 5183776
    Abstract: Preferred embodiments disclose include methods of fabrication and integrated circuits (30) in GaAs layers (38, 40) on silicon substrates (32) with the gallium arsenide grown by MBE or MOCVD and containing thermally-strained superlattices (36) and post-growth high temperature annealing to lower defect density. The annealing confines dislocations to a thin network at the interface of the GaAs buffer layer (34) and the silicon substrate (32).
    Type: Grant
    Filed: August 3, 1989
    Date of Patent: February 2, 1993
    Assignee: Texas Instruments Incorporated
    Inventor: Jhang W. Lee
  • III-V Semiconductor growth initiation on silicon using TMG and TEG
    Patent number: 4910167
    Abstract: A GaAs containing nucleation layer is deposited upon Si, Ge/Si, or other single crystal substrate from triethyl gallium (TEG). Deposition from TEG allows a lower deposition temperature which provides a low level of substrate contamination and improved surface morphology.
    Type: Grant
    Filed: November 13, 1987
    Date of Patent: March 20, 1990
    Assignee: Kopin Corporation
    Inventors: Jhang W. Lee, Richard E. McCullough, Jack P. Salerno
  • III-V on Si heterostructure using a thermal strain layer
    Patent number: 4900372
    Abstract: A method for producing wafers having deposited layers of III-V materials on Si or Ge/Si substrates is disclosed. The method involves the use of multiple in situ and ex situ annealing steps and the formation of a thermal strain layer to produce wafers having a decreased incidence of defects and a balanced thermal strain. The wafers produced thereby are also disclosed.
    Type: Grant
    Filed: March 2, 1989
    Date of Patent: February 13, 1990
    Assignee: Kopin Corporation
    Inventors: Jhang W. Lee, Richard E. McCullough
  • Ion implantation and annealing of compound semiconductor layers
    Patent number: 4863877
    Abstract: A method for reducing the defect and dislocation density in III-V material layers deposited on dissimilar substrates is disclosed. The method involves ion implantation of dopant materials to create amorphous regions within the layers followed by an annealing step during which the amorphous regions are recrystallized to form substantially monocrystalline regions. The wafers produced by the process are particularly well suited for optoelectronic devices.
    Type: Grant
    Filed: November 13, 1987
    Date of Patent: September 5, 1989
    Assignee: Kopin Corporation
    Inventors: John C. C. Fan, Jhang W. Lee, Jagdish Narayan
  • Binary superlattice tunneling device and method
    Patent number: 4851886
    Abstract: A resonant tunneling diode (30) with anode (40) and cathode (32) separated by binary short-period superlattice tunneling barriers (34,38) with a quantum well (36) between is disclosed. Enhancement and depletion mode diodes are disclosed.
    Type: Grant
    Filed: June 11, 1986
    Date of Patent: July 25, 1989
    Assignee: Texas Instruments Incorporated
    Inventors: Jhang W. Lee, Mark A. Reed
  • Annealing method for III-V deposition
    Patent number: 4835116
    Abstract: A method for producing wafers having deposited layers of III-V materials on Si or Ge/Si substrates is disclosed. The method involves the use of multiple in situ and ex situ annealing steps and the formation of a thermal strain layer to produce wafers having a decreased incidence of defects and a balanced thermal strain. The wafers produced thereby are also disclosed.
    Type: Grant
    Filed: November 13, 1987
    Date of Patent: May 30, 1989
    Assignee: Kopin Corporation
    Inventors: Jhang W. Lee, Richard E. McCullough
  • Selective OMCVD growth of compound semiconductor materials on silicon substrates
    Patent number: 4826784
    Abstract: A method of OMCVD heteroepitaxy of III/V (GaAs) material on a patterned Si substrate is described wherein heteroepitaxy deposition occurs only on the exposed Si surfaces and nowhere else.
    Type: Grant
    Filed: November 13, 1987
    Date of Patent: May 2, 1989
    Assignee: Kopin Corporation
    Inventors: Jack P. Salerno, Jhang W. Lee, Richard E. McCullough