Patents by Inventor Jhen-Siang Wu

Jhen-Siang Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • LAYOUT PATTERN FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY
    Publication number: 20210183944
    Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a first magnetic tunneling junction (MTJ) pattern on a substrate, a second MTJ pattern adjacent to the first MTJ pattern, and a third MTJ pattern between the first MTJ pattern and the second MTJ pattern. Preferably, the first MTJ pattern, the second MTJ pattern, and the third MTJ pattern constitute a staggered arrangement.
    Type: Application
    Filed: January 20, 2020
    Publication date: June 17, 2021
    Inventors: Yi-Ting Wu, Jian-Jhong Chen, Po-Chun Yang, Jhen-Siang Wu, Yung-Ching Hsieh, Bo-Chang Li, Jen-Yu Wang, Cheng-Tung Huang
  • Layout pattern for magnetoresistive random access memory
    Patent number: 11018185
    Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a first magnetic tunneling junction (MTJ) pattern on a substrate, a second MTJ pattern adjacent to the first MTJ pattern, and a third MTJ pattern between the first MTJ pattern and the second MTJ pattern. Preferably, the first MTJ pattern, the second MTJ pattern, and the third MTJ pattern constitute a staggered arrangement.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: May 25, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Ting Wu, Jian-Jhong Chen, Po-Chun Yang, Jhen-Siang Wu, Yung-Ching Hsieh, Bo-Chang Li, Jen-Yu Wang, Cheng-Tung Huang
  • Memory including non-volatile cells and current driving circuit
    Patent number: 10978122
    Abstract: A memory includes (n?1) non-volatile cells, (n?1) bit lines and a current driving circuit. Each of the (n?1) non-volatile cells includes a first terminal and a second terminal. An ith bit line of the (n?1) bit lines is coupled to a first terminal of an ith non-volatile cell of the (n?1) non-volatile cells. The current driving circuit includes n first transistors coupled to the (n?1) non-volatile cells.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: April 13, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yen Tseng, Yu-Tse Kuo, Chang-Hung Chen, Shu-Ru Wang, Ya-Lan Chiou, Chun-Hsien Huang, Chih-Wei Tsai, Hsin-Chih Yu, Yi-Ting Wu, Cheng-Tung Huang, Jen-Yu Wang, Jhen-Siang Wu, Po-Chun Yang, Yung-Ching Hsieh, Jian-Jhong Chen, Bo-Chang Li
  • 2-transistor 2-magnetic tunnel junction (2T2MTJ) MRAM structure
    Patent number: 10651235
    Abstract: A first MRAM set includes a first transistor and a second transistor. The first transistor includes a first gate structure, a first source/drain doping region and a first common source/drain doping region. The second transistor includes a second gate structure, a second source/drain doping region and the first common source/drain doping region. A second MTJ is disposed on the second transistor. The first common source/drain doping region electrically connects to the second MTJ. A first MTJ is disposed on the first transistor. The sizes of the first MTJ and the second MTJ are different. The second MTJ connects to the first MTJ in series. A bit line electrically connects the first MTJ. A source line electrically connects to the first source/drain doping region and the second source/drain doping region.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: May 12, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Ting Wu, Jhen-Siang Wu, Po-Chun Yang, Yung-Ching Hsieh, Zong-Sheng Zheng, Jian-Jhong Chen, Jen-Yu Wang, Cheng-Tung Huang