Abstract: A semiconductor device includes a bit line, a source, a body, a channel, a drain, a word line and a first body contact. The source is on the bit line. The body is on the source. The channel is on the body. The drain is on the channel. The word line surrounds and is spaced apart from the channel. The first body contact is on the body, in which the first body contact and the source are separated by the body.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a substrate having a trench and a gate structure in the trench. The trench includes a lower gate electrode, an upper gate electrode over the lower gate electrode and a first dielectric layer partially disposed between the lower gate electrode and the upper gate electrode.

Abstract: A memory device comprises a substrate; a first word line structure, a first dielectric layer; a dielectric liner, and a bit line structure. The first word line structure is in the substrate and comprises a first bottom conductive material and a first top conductive material, in which a top surface of the first bottom conductive material is wider than a bottom surface of the first top conductive material. The first dielectric layer is over the first word line structure. The dielectric liner lines the first word line structure. The bit line structure is over the substrate.

Abstract: A semiconductor device with a passing gate is provided. The semiconductor device includes a substrate having a first trench and a first gate structure in the first trench. The first gate structure includes a first gate electrode having a first doped region.

Abstract: The present application discloses a contact structure, a semiconductor device including the contact structure, and a method for fabricating the semiconductor device. The contact structure includes a body portion; and an extending portion downwardly extending from the body portion and comprising a groove. The groove is recessed from a bottom surface of the extending portion, leading towards the body portion, and exposing the body portion.

Abstract: The present application discloses a contact structure, a semiconductor device including the contact structure, and a method for fabricating the semiconductor device. The contact structure includes a body portion; and an extending portion downwardly extending from the body portion and including a groove. The groove is recessed from a bottom surface of the extending portion, leading towards the body portion, and exposing the body portion.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a trench in a substrate; disposing an upper gate electrode in the trench; disposing a first dielectric layer on the upper gate electrode in the trench; and disposing a capping layer on the first dielectric layer in the trench.

Abstract: A memory device includes a substrate, a capacitor, a transistor, a word line, a bit line contact and a body contact. The capacitor is over the substrate. The transistor is over the capacitor, and the transistor includes a channel region, a gate over the channel region, and a source and a drain on opposite sides of the channel region, in which the drain is over the capacitor. The word line is over and electrically connected to the gate of the transistor. The bit line contact is over and electrically connected to the source of the transistor. The body contact is below the source of the transistor.

Abstract: A manufacturing method of a memory device includes forming a capacitor in a first dielectric layer, and forming a bottom electrode over the capacitor. A word line and a second dielectric layer are formed over the bottom electrode and the first dielectric layer, in which the word line is embedded in the second dielectric layer. A bit line contact is formed over the second dielectric layer, in which a vertical projection of the bit line contact on the first dielectric layer is spaced apart a vertical projection of the bottom electrode on the first dielectric layer. After forming the bit line contact, a channel in contact with the bottom electrode and the word line is formed. A top electrode is formed over the channel and in contact with the bit line contact.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a trench in a substrate; disposing an upper gate electrode in the trench; disposing a first dielectric layer on the upper gate electrode in the trench; and disposing a capping layer on the first dielectric layer in the trench.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a buried conductive layer including a bottom portion positioned in the substrate, and a top portion positioned in the substrate and positioned on the bottom portion; and an in-recess spacer positioned in the substrate, surrounding the bottom portion, and covered by the top portion. A top surface of the top portion and a top surface of the substrate are substantially coplanar. A bottom surface of the in-recess spacer and a bottom surface of the bottom portion are substantially coplanar. A sidewall of the in-recess spacer and a sidewall of the top portion are substantially coplanar.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a buried conductive layer including a bottom portion positioned in the substrate, and a top portion positioned in the substrate and positioned on the bottom portion; and an in-recess spacer positioned in the substrate, surrounding the bottom portion, and covered by the top portion. A top surface of the top portion and a top surface of the substrate are substantially coplanar. A bottom surface of the in-recess spacer and a bottom surface of the bottom portion are substantially coplanar. A sidewall of the in-recess spacer and a sidewall of the top portion are substantially coplanar.

Abstract: A semiconductor device manufacturing method includes the following steps. A well implant process is performed on a region of a substrate. A source/drain implant process is performed on the region of the substrate. An active area is defined on the region of the substrate. Shallow trench isolations are formed in the active area. An annealing process is performed to the region of the substrate.

Abstract: A semiconductor device includes a first vertical transistor and a second vertical transistor adjacent to the first vertical transistor. The first vertical transistor includes a first channel region, a first word line wrapping the first channel region, and a first word line dielectric layer between the first channel region and the first word line. The second vertical transistor includes a second channel region, a second word line wrapping the second channel region, and a second word line dielectric layer between the second channel region and the second word line. The semiconductor device further includes a dielectric layer wrapping upper portions of the first word line and the second word line, and an air gap inserted between lower portions of the first vertical transistor and the second vertical transistor.

Abstract: A semiconductor device includes a substrate, a first word line, a barrier layer, a first insulating layer and a second insulating layer. The first word line is in the substrate. The barrier layer cups an underside of the first word line. The first insulating layer extends along a top surface of the first word line and is laterally surrounded by the barrier layer. The second insulating layer is on the first insulating layer and laterally surrounded by the barrier layer. The second insulating layer has a material different from a material of the first insulating layer.

Abstract: A semiconductor device includes a channel structure, a dielectric structure, a gate structure, a first conductive structure, and a second conductive structure. The channel structure has a top surface, a bottom surface, and a sidewall extending from the top surface to the bottom surface. The first conductive structure is disposed on the bottom surface of the channel structure and includes a body portion and at least one convex portion, and a top surface of the convex portion is higher than a top surface of the body portion. The second conductive structure is disposed on the top surface of the channel structure and includes a body portion and at least one convex portion, and a bottom surface of the body portion is higher than a bottom surface of the convex portion.

Abstract: A semiconductor structure includes a substrate, a first isolation layer and a source. The substrate has a body portion and a protruding portion extending from the body portion. The first isolation layer is located on the body portion of the substrate. The source is located on the first isolation layer. The source has a first portion and a second portion opposite to the first portion. The protruding portion of the substrate is located between the first portion and the second portion of the source.

Abstract: A method of manufacturing a semiconductor device includes providing a precursor structure including a first capacitor and a second capacitor on a substrate; forming a first vertical transistor and a second vertical transistor respectively over the first capacitor and the second capacitor, in which the first vertical transistor includes a first word line having a first top width and a first bottom width smaller than the first top width, the second vertical transistor includes a second word line having a second top width and a second bottom width smaller than the second top width; and forming an air gap between the first vertical transistor and the second vertical transistor.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes: a first doped structure over a substrate and a second doped structure over the first doped structure and the substrate; a first gate layer, at last partially disposed between the first doped structure and the second doped structure; a first gate dielectric layer, surrounding the first gate layer; a channel layer, surrounding the first gate dielectric layer; a second gate dielectric layer, surrounding the channel layer; and a second gate layer, surrounding the second gate dielectric layer. A manufacturing method for forming the same is also provided.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes: a first doped structure over a substrate and a second doped structure over the first doped structure and the substrate; a first gate layer, at last partially disposed between the first doped structure and the second doped structure; a first gate dielectric layer, surrounding the first gate layer; a channel layer, surrounding the first gate dielectric layer; a second gate dielectric layer, surrounding the channel layer; and a second gate layer, surrounding the second gate dielectric layer. A manufacturing method for forming the same is also provided.