Patents by Inventor JHEN-YU TSAI

JHEN-YU TSAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11563007
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure comprises a substrate, a cell capacitor, a channel structure, a lining material, a word line and a bit line. The cell capacitor is disposed over the substrate. The channel structure is disposed over the cell capacitor, wherein the channel structure comprises a horizontal member and at least two vertical members extending from the horizontal member and separated by a ditch on the horizontal member. The lining material surrounds each of the at least two vertical members. The word line encloses the at least two vertical members and partially fills the ditch. The bit line is disposed over the channel structure.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: January 24, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Jhen-Yu Tsai
  • Publication number: 20220344335
    Abstract: A method includes forming a first conductive line and a second conductive respectively above a memory region and a peripheral region of a substrate. A capacitor is formed above the first conductive line. A bottom portion of a contact structure is formed above the second conductive line. A first dielectric layer is formed covering the capacitor and the bottom portion. First and second openings are formed in the first dielectric layer. The first opening is above the capacitor, and the second opening exposes the bottom portion. A middle portion of the contact structure and a gate material are respectively formed in the second opening and the first opening. A third opening is formed in the gate material to form a gate structure. A gate dielectric layer and a channel are formed in the third opening. A bit line is connected to the channel and the contact structure.
    Type: Application
    Filed: July 6, 2022
    Publication date: October 27, 2022
    Inventor: Jhen-Yu TSAI
  • Patent number: 11482419
    Abstract: The present disclosure provides a transistor device and a method for preparing the same. The transistor device includes an isolation structure disposed in a substrate, an active region disposed in the substrate and surrounded by the isolation structure, a first upper gate disposed over the active region and a portion of the isolation structure, a source/drain disposed at two sides of the gate, and a pair of first lower gates disposed under the first upper gate and isolated from the active region by the isolation structure. In some embodiments, the pair of first lower gates extend in a first direction, the first upper gate extends in a second direction, and the first direction and the second direction are different.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: October 25, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Jhen-Yu Tsai, Tseng-Fu Lu, Wei-Ming Liao
  • Publication number: 20220293604
    Abstract: The present disclosure provides a method of fabricating a semiconductor structure. The method comprises providing a substrate; forming a cell capacitor over the substrate; forming a channel material over the cell capacitor; cutting the channel material to form a channel structure, wherein the channel structure comprises a horizontal member and at least two vertical members separated by a ditch on the horizontal member; forming a lining material on sidewalls of the at least two vertical members; forming a word line to enclose the at least two vertical members encircled by the lining material, and partially fill the ditch; and forming a bit line over the channel structure.
    Type: Application
    Filed: May 31, 2022
    Publication date: September 15, 2022
    Inventor: JHEN-YU TSAI
  • Patent number: 11417662
    Abstract: A memory device includes a substrate, a conductive line, a capacitor, a transistor, and a contact structure. The conductive line is above a peripheral region of the substrate. The capacitor is above a memory region of the substrate. The transistor is above and connected to the capacitor and includes first and second source/drain regions, a channel, and a gate structure. The first source/drain region is connected to the capacitor. The gate structure laterally surrounds the channel. The contact structure is above the peripheral region and includes a bottom portion, a top portion, and a middle portion. The bottom portion is connected to the conductive line. The top portion is connected to the second source/drain region. The middle portion is wider than the top portion and the bottom portion, in which the middle portion of the contact structure is at a height substantially level with the gate structure.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: August 16, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Jhen-Yu Tsai
  • Publication number: 20220130832
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure comprises a substrate, a cell capacitor, a channel structure, a lining material, a word line and a bit line. The cell capacitor is disposed over the substrate. The channel structure is disposed over the cell capacitor, wherein the channel structure comprises a horizontal member and at least two vertical members extending from the horizontal member and separated by a ditch on the horizontal member. The lining material surrounds each of the at least two vertical members. The word line encloses the at least two vertical members and partially fills the ditch. The bit line is disposed over the channel structure.
    Type: Application
    Filed: October 26, 2020
    Publication date: April 28, 2022
    Inventor: JHEN-YU TSAI
  • Publication number: 20220068926
    Abstract: A method of manufacturing a semiconductor device includes providing a precursor structure including a first capacitor and a second capacitor on a substrate; forming a first vertical transistor and a second vertical transistor respectively over the first capacitor and the second capacitor, in which the first vertical transistor includes a first word line having a first top width and a first bottom width smaller than the first top width, the second vertical transistor includes a second word line having a second top width and a second bottom width smaller than the second top width; and forming an air gap between the first vertical transistor and the second vertical transistor.
    Type: Application
    Filed: November 10, 2021
    Publication date: March 3, 2022
    Inventor: Jhen-Yu TSAI
  • Publication number: 20220068924
    Abstract: A memory device includes a substrate, a conductive line, a capacitor, a transistor, and a contact structure. The conductive line is above a peripheral region of the substrate. The capacitor is above a memory region of the substrate. The transistor is above and connected to the capacitor and includes first and second source/drain regions, a channel, and a gate structure. The first source/drain region is connected to the capacitor. The gate structure laterally surrounds the channel. The contact structure is above the peripheral region and includes a bottom portion, a top portion, and a middle portion. The bottom portion is connected to the conductive line. The top portion is connected to the second source/drain region. The middle portion is wider than the top portion and the bottom portion, in which the middle portion of the contact structure is at a height substantially level with the gate structure.
    Type: Application
    Filed: August 25, 2020
    Publication date: March 3, 2022
    Inventor: Jhen-Yu TSAI
  • Publication number: 20220045073
    Abstract: The present application provides a method for preparing a memory device. The method includes: forming an active region in a substrate, wherein the active region has a linear top view shape; forming a gate structure on the substrate, wherein the gate structure has a linear portion intersected with a section of the active region away from end portions of the active region; forming a first insulating layer and a second insulating layer on the substrate, wherein the first insulating layer laterally surrounds the gate structure, and is covered by the second insulating layer; forming an opening penetrating through the first and second insulating layers and exposing a portion of the active region, wherein the opening is laterally spaced apart from the gate structure; and sequentially forming a dielectric layer and an electrode in the opening.
    Type: Application
    Filed: August 10, 2020
    Publication date: February 10, 2022
    Inventors: Chin-Ling HUANG, Jhen-Yu TSAI, Cheng-Han YANG, Yi-Ju CHEN
  • Patent number: 11244950
    Abstract: The present application provides a method for preparing a memory device. The method includes: forming an active region in a substrate, wherein the active region has a linear top view shape; forming a gate structure on the substrate, wherein the gate structure has a linear portion intersected with a section of the active region away from end portions of the active region; forming a first insulating layer and a second insulating layer on the substrate, wherein the first insulating layer laterally surrounds the gate structure, and is covered by the second insulating layer; forming an opening penetrating through the first and second insulating layers and exposing a portion of the active region, wherein the opening is laterally spaced apart from the gate structure; and sequentially forming a dielectric layer and an electrode in the opening.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: February 8, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chin-Ling Huang, Jhen-Yu Tsai, Cheng-Han Yang, Yi-Ju Chen
  • Patent number: 11217589
    Abstract: A semiconductor device includes a first vertical transistor, a second vertical transistor adjacent to the first vertical transistor, and an air gap inserted between the first vertical transistor and the second vertical transistor. The first vertical transistor includes a first channel region, a first word line wrapping the first channel region, and a first word line dielectric layer between the first channel region and the first word line. The second vertical transistor includes a second channel region, a second word line wrapping the second channel region, and a second word line dielectric layer between the second channel region and the second word line. The first word line and the second word line respectively have a top width and a bottom width, and the top width is greater than the bottom width.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: January 4, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Jhen-Yu Tsai
  • Patent number: 11205651
    Abstract: Provided are a memory structure and a method for manufacturing the same. The memory structure includes a capacitor and a transistor disposed thereon and electrically connected thereto. The transistor includes a first and a source/drain layers, a channel pillar, a gate, a gate dielectric layer, a doped layer, and a spacer layer. The first source/drain layer is electrically connected to the capacitor. The channel pillar is on the first source/drain layer. The gate is on a sidewall of the channel pillar. The gate dielectric layer is between the gate and the channel pillar. The doped layer is on the sidewall of the channel pillar and above the gate. The spacer layer is between the gate and the first source/drain layer and between the gate and the doped layer. The second source/drain layer is on or in the channel pillar.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: December 21, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Jhen-Yu Tsai
  • Publication number: 20210376165
    Abstract: A semiconductor device includes a channel structure, a dielectric structure, a gate structure, a first conductive structure, and a second conductive structure. The channel structure has a top surface, a bottom surface, and a sidewall extending from the top surface to the bottom surface. The first conductive structure is disposed on the bottom surface of the channel structure and includes a body portion and at least one convex portion, and a top surface of the convex portion is higher than a top surface of the body portion. The second conductive structure is disposed on the top surface of the channel structure and includes a body portion and at least one convex portion, and a bottom surface of the body portion is higher than a bottom surface of the convex portion.
    Type: Application
    Filed: August 11, 2021
    Publication date: December 2, 2021
    Inventor: Jhen-Yu TSAI
  • Patent number: 11127859
    Abstract: A semiconductor device includes a channel structure, a dielectric structure, a gate structure, a first conductive structure, and a second conductive structure. The channel structure has a top surface, a bottom surface, and a sidewall extending from the top surface to the bottom surface. The first conductive structure is disposed on the bottom surface of the channel structure and includes a body portion and at least one convex portion, and a top surface of the convex portion is higher than a top surface of the body portion. The second conductive structure is disposed on the top surface of the channel structure and includes a body portion and at least one convex portion, and a bottom surface of the body portion is higher than a bottom surface of the convex portion.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: September 21, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Jhen-Yu Tsai
  • Publication number: 20210265358
    Abstract: Provided are a memory structure and a method for manufacturing the same. The memory structure includes a capacitor and a transistor disposed thereon and electrically connected thereto. The transistor includes a first and a source/drain layers, a channel pillar, a gate, a gate dielectric layer, a doped layer, and a spacer layer. The first source/drain layer is electrically connected to the capacitor. The channel pillar is on the first source/drain layer. The gate is on a sidewall of the channel pillar. The gate dielectric layer is between the gate and the channel pillar. The doped layer is on the sidewall of the channel pillar and above the gate. The spacer layer is between the gate and the first source/drain layer and between the gate and the doped layer. The second source/drain layer is on or in the channel pillar.
    Type: Application
    Filed: February 24, 2020
    Publication date: August 26, 2021
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventor: Jhen-Yu Tsai
  • Publication number: 20210210609
    Abstract: The present disclosure provides a method for manufacturing a semiconductor device. The method includes steps of forming a recess in the substrate; depositing an insulating layer on the substrate; forming a gate electrode on the insulating layer and partly buried in the recess; removing a portion of the insulating layer exposed through the gate electrode to form a gate dielectric; and implanting dopants in the substrate to form a source region and a drain region on either side of the gate electrode.
    Type: Application
    Filed: March 16, 2021
    Publication date: July 8, 2021
    Inventor: Jhen-Yu TSAI
  • Patent number: 10998319
    Abstract: Provided is a memory structure including a substrate having a memory region and a peripheral region, a capacitor array, a transistor array, bit lines, and contacts. The capacitor array is on the substrate in the memory region. The transistor array is on and electrically connected to the capacitor array. The bit lines are extended along a row direction in parallel with each other on the transistor array, and are electrically connected to the transistor array. Each of the contacts is connected to one of the bit lines and a conductive device at the substrate in the peripheral region. Each of the contacts includes a first portion, a second portion, and a third portion. The second portion is between the first portion and the third portion. The third portion is electrically connected to the conductive device. Distances between each of the third portions and the memory region are the same.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: May 4, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Jhen-Yu Tsai
  • Patent number: 10985254
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a source region, a drain region, and a gate electrode. The source region and the drain region are in the substrate, and the gate electrode is partly buried in the substrate and between the source region and the drain region.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: April 20, 2021
    Assignee: Nanya Technology Corporation
    Inventor: Jhen-Yu Tsai
  • Publication number: 20210104525
    Abstract: A semiconductor device includes a first vertical transistor, a second vertical transistor adjacent to the first vertical transistor, and an air gap inserted between the first vertical transistor and the second vertical transistor. The first vertical transistor includes a first channel region, a first word line wrapping the first channel region, and a first word line dielectric layer between the first channel region and the first word line. The second vertical transistor includes a second channel region, a second word line wrapping the second channel region, and a second word line dielectric layer between the second channel region and the second word line. The first word line and the second word line respectively have a top width and a bottom width, and the top width is greater than the bottom width.
    Type: Application
    Filed: October 4, 2019
    Publication date: April 8, 2021
    Inventor: Jhen-Yu TSAI
  • Publication number: 20210082705
    Abstract: The present disclosure provides a transistor device and a method for preparing the same. The transistor device includes an isolation structure disposed in a substrate, an active region disposed in the substrate and surrounded by the isolation structure, a first upper gate disposed over the active region and a portion of the isolation structure, a source/drain disposed at two sides of the gate, and a pair of first lower gates disposed under the first upper gate and isolated from the active region by the isolation structure. In some embodiments, the pair of first lower gates extend in a first direction, the first upper gate extends in a second direction, and the first direction and the second direction are different.
    Type: Application
    Filed: November 30, 2020
    Publication date: March 18, 2021
    Inventors: JHEN-YU TSAI, TSENG-FU LU, WEI-MING LIAO