Patents by Inventor JHENG HAO FANG

JHENG HAO FANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Structure of epitaxy on heterogeneous substrate and method for fabricating the same
    Patent number: 11232950
    Abstract: The invention is a special designed pattern heterogeneous substrate, which is epitaxially deposited on a heterogeneous substrate by two step growth, and a thermal cycle annealing is added to reduce the lattice mismatch between the layers and the difference in thermal expansion coefficient, thereby obtaining a better stress. The quality of the semiconductor epitaxial layer is improved, and the present invention can easily grasp the timing of stress release when the semiconductor is grown on the heterogeneous substrate, avoid cracks in the semiconductor epitaxial layer, and form a crack free zone in the middle of the semiconductor epitaxial layer.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: January 25, 2022
    Assignee: Institute of Nuclear Energy Research, Atomic Energy Council, Executive Yuan, R.O.C.
    Inventors: Jheng Hao Fang, Yu Li Tsai, Hsueh-Hui Yang, Chih Hung Wu, Hwen Fen Hong
  • STRUCTURE OF EPITAXY ON HETEROGENEOUS SUBSTRATE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20200343093
    Abstract: The invention is a special designed pattern heterogeneous substrate, which is epitaxially deposited on a heterogeneous substrate by two step growth, and a thermal cycle annealing is added to reduce the lattice mismatch between the layers and the difference in thermal expansion coefficient, thereby obtaining a better stress. The quality of the semiconductor epitaxial layer is improved, and the present invention can easily grasp the timing of stress release when the semiconductor is grown on the heterogeneous substrate, avoid cracks in the semiconductor epitaxial layer, and form a crack free zone in the middle of the semiconductor epitaxial layer.
    Type: Application
    Filed: November 1, 2019
    Publication date: October 29, 2020
    Inventors: JHENG HAO FANG, YU LI TSAI, HSUEH-HUI YANG, CHIH HUNG WU, HWEN FEN HONG