Patents by Inventor Jhi-Cherng Lu

Jhi-Cherng Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9011599
    Abstract: A method of determining a temperature in a deposition reactor includes the steps of depositing a first epitaxial layer of silicon germanium on a substrate, depositing a second epitaxial layer of silicon above the first epitaxial layer, measuring the thickness of the second epitaxial layer and determining the temperature in the deposition reactor using the measured thickness of the second epitaxial layer. The method may also include heating the deposition reactor to approximately a predetermined temperature using a heating device and a temperature measuring device and generating a signal indicative of a temperature within the deposition reactor. The method may also contain the steps of comparing the measured thickness with a predetermined thickness of the second epitaxial layer corresponding to the predetermined temperature and determining the temperature in the deposition reactor using the measured thickness of the second epitaxial layer and the predetermined thickness of the second epitaxial layer.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: April 21, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jhi-Cherng Lu, Jr-Hung Li, Chii-Horng Li, Pang-Yen Tsai, Bing-Hung Chen, Tze-Liang Lee
  • Patent number: 8530316
    Abstract: A method for fabricating a semiconductor device, the method including growing a first semiconductor structure comprising a first semiconductor material on a surface of a substrate, wherein growing the first semiconductor structure includes forming a semiconductor particle comprising the first semiconductor material on a second semiconductor structure of the semiconductor device. The method further includes forming a protection layer of a second semiconductor material on the first semiconductor structure, wherein forming the protection layer includes forming the protection layer on the semiconductor particle. The method further includes removing a portion of the protection layer, wherein removing the portion of the protection layer includes fully removing the protection layer on the semiconductor particle and the semiconductor particle.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: September 10, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Cheng, Jhi-Cherng Lu, Ming-Hua Yu, Chii-Horng Li, Tze-Liang Lee
  • Publication number: 20130122675
    Abstract: A method for fabricating a semiconductor device, the method including growing a first semiconductor structure comprising a first semiconductor material on a surface of a substrate, wherein growing the first semiconductor structure includes forming a semiconductor particle comprising the first semiconductor material on a second semiconductor structure of the semiconductor device. The method further includes forming a protection layer of a second semiconductor material on the first semiconductor structure, wherein forming the protection layer includes forming the protection layer on the semiconductor particle. The method further includes removing a portion of the protection layer, wherein removing the portion of the protection layer includes fully removing the protection layer on the semiconductor particle and the semiconductor particle.
    Type: Application
    Filed: January 8, 2013
    Publication date: May 16, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung CHENG, Jhi-Cherng LU, Ming-Hua YU, Chii-Horng LI, Tze-Liang LEE
  • Patent number: 8377784
    Abstract: The present disclosure discloses an exemplary method for fabricating a semiconductor device comprises selectively growing a material on a top surface of a substrate; selectively growing a protection layer on the material; and removing a portion of the protection layer in an etching gas.
    Type: Grant
    Filed: April 22, 2010
    Date of Patent: February 19, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Cheng, Jhi-Cherng Lu, Ming-Hua Yu, Chii-Horng Li, Tze-Liang Lee
  • Publication number: 20120012047
    Abstract: A method of determining a temperature in a deposition reactor includes the steps of depositing a first epitaxial layer of silicon germanium on a substrate, depositing a second epitaxial layer of silicon above the first epitaxial layer, measuring the thickness of the second epitaxial layer and determining the temperature in the deposition reactor using the measured thickness of the second epitaxial layer. The method may also include heating the deposition reactor to approximately a predetermined temperature using a heating device and a temperature measuring device and generating a signal indicative of a temperature within the deposition reactor. The method may also contain the steps of comparing the measured thickness with a predetermined thickness of the second epitaxial layer corresponding to the predetermined temperature and determining the temperature in the deposition reactor using the measured thickness of the second epitaxial layer and the predetermined thickness of the second epitaxial layer.
    Type: Application
    Filed: July 14, 2010
    Publication date: January 19, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jhi-Cherng LU, Jr-Hung LI, Chii-Horng LI, Pang-Yen TSAI, Bing-Hung CHEN, Tze-Liang LEE
  • Publication number: 20110263092
    Abstract: The present disclosure discloses an exemplary method for fabricating a semiconductor device comprises selectively growing a material on a top surface of a substrate; selectively growing a protection layer on the material; and removing a portion of the protection layer in an etching gas.
    Type: Application
    Filed: April 22, 2010
    Publication date: October 27, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Hung CHENG, Jhi-Cherng LU, Ming-Hua YU, Chii-Horng LI, Tze-Liang LEE
  • Patent number: 7663185
    Abstract: A fin-FET device and a method for fabrication thereof both employ a bulk semiconductor substrate. A fin and an adjoining trough are formed within the bulk semiconductor substrate. The trough is partially backfilled with a deposited dielectric layer to form an exposed fin region and an unexposed fin region. A gate dielectric layer is formed upon the exposed fin region and a gate electrode is formed upon the gate dielectric layer. By employing a bulk semiconductor substrate the fin-FET device is fabricated cost effectively.
    Type: Grant
    Filed: May 27, 2006
    Date of Patent: February 16, 2010
    Assignee: Taiwan Semiconductor Manufacturing Co, Ltd
    Inventors: Kuang-Hsin Chen, Hsun-Chih Tsao, Jhi-Cherng Lu, Chuan-Ping Hou, Peng-Fu Hsu, Hung-Wei Chen, Di-Hong Lee
  • Patent number: 7332777
    Abstract: In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer is formed on the patterned silicon layer. A first layer is formed on the initial structure. Part of the first layer is removed with an etching process, such that a sidewall portion of the patterned silicon layer is exposed and such that a remaining portion of the first layer remains at a corner where the patterned silicon layer interfaces with the buried insulator layer. An oxide liner is formed on the exposed sidewall portion. A recess may be formed in the buried insulator layer (prior to forming the first layer) and may extend partially beneath the patterned silicon layer.
    Type: Grant
    Filed: September 7, 2005
    Date of Patent: February 19, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuang-Hsin Chen, Hsun-Chih Tsao, Hung-Wei Chen, Di-Hong Lee, Chuan-Ping Hou, Jhi-Cherng Lu
  • Publication number: 20070272954
    Abstract: A fin-FET device and a method for fabrication thereof both employ a bulk semiconductor substrate. A fin and an adjoining trough are formed within the bulk semiconductor substrate. The trough is partially backfilled with a deposited dielectric layer to form an exposed fin region and an unexposed fin region. A gate dielectric layer is formed upon the exposed fin region and a gate electrode is formed upon the gate dielectric layer. By employing a bulk semiconductor substrate the fin-FET device is fabricated cost effectively.
    Type: Application
    Filed: May 27, 2006
    Publication date: November 29, 2007
    Inventors: Kuang-Hsin Chen, Hsun-Chih Tsao, Jhi-Cherng Lu, Chuan-Ping Hou, Peng-Fu Hsu, Hung-Wei Chen, Di-Hong Lee
  • Patent number: 7026196
    Abstract: A method for forming a field effect transistor includes: forming a conductive region on an isolation layer formed on a substrate, and a cap dielectric layer on the conductive region; forming a sacrificial dielectric layer over the isolation layer and the cap dielectric layer, and on sidewalls of the conductive region; removing a portion of the sacrificial dielectric layer on the cap dielectric layer; removing the cap dielectric layer; removing remaining portions of the sacrificial dielectric layer; forming a gate on the conductive region; and forming source/drain (S/D) regions within the conductive region and adjacent to the gate. A field effect transistor includes a conductive region over an isolation layer formed on a substrate, the conductive region being substantially without undercut at the region within the isolation layer beneath the conductive region; a gate on the conductive region; and S/D regions within the conductive region and adjacent to the gate.
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: April 11, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chuan-Ping Hou, Jhi-Cherng Lu, Kuang-Hsin Chen, Hsun-Chih Tsao
  • Publication number: 20060049036
    Abstract: A method comprises measuring an RF voltage and ion current at a wafer during a plasma-enhanced deposition process, determining a sputter rate in response to the RF voltage and ion current measurements, detecting an abnormal condition in response to one of the RF voltage and ion current measurements, and sputter rate, and taking a corrective action in response to detecting an abnormal condition.
    Type: Application
    Filed: September 9, 2004
    Publication date: March 9, 2006
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hung Chang, Jhi-Cherng Lu, Joung-Wei Liou, Chu-Yun Fu, Weng Chang, Syung-Ming Jang
  • Publication number: 20060012004
    Abstract: In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer is formed on the patterned silicon layer. A first layer is formed on the initial structure. Part of the first layer is removed with an etching process, such that a sidewall portion of the patterned silicon layer is exposed and such that a remaining portion of the first layer remains at a corner where the patterned silicon layer interfaces with the buried insulator layer. An oxide liner is formed on the exposed sidewall portion. A recess may be formed in the buried insulator layer (prior to forming the first layer) and may extend partially beneath the patterned silicon layer.
    Type: Application
    Filed: September 7, 2005
    Publication date: January 19, 2006
    Inventors: Kuang-Hsin Chen, Hsun-Chih Tsao, Hung-Wei Chen, Di-Hong Lee, Chuan-Ping Hou, Jhi-Cherng Lu
  • Patent number: 6955955
    Abstract: In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer is formed on the patterned silicon layer. A first layer is formed on the initial structure. Part of the first layer is removed with an etching process, such that a sidewall portion of the patterned silicon layer is exposed and such that a remaining portion of the first layer remains at a corner where the patterned silicon layer interfaces with the buried insulator layer. An oxide liner is formed on the exposed sidewall portion. A recess may be formed in the buried insulator layer (prior to forming the first layer) and may extend partially beneath the patterned silicon layer.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: October 18, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuang-Hsin Chen, Hsun-Chih Tsao, Hung-Wei Chen, Di-Hong Lee, Chuan-Ping Hou, Jhi-Cherng Lu
  • Publication number: 20050170606
    Abstract: A shallow trench isolation (STI) structure and method of forming the same with reduced stress to improve charge mobility the method including providing a semiconductor substrate comprising at least one patterned hardmask layer overlying the semiconductor substrate; dry etching a trench in the semiconductor substrate according to the at least one patterned hardmask layer; forming one or more liner layers to line the trench selected from the group consisting of silicon dioxide, silicon nitride, and silicon oxynitride; forming one or more layers of trench filling material comprising silicon dioxide to backfill the trench; carrying out at least one thermal annealing step to relax accumulated stress in the trench filling material; carrying out at least one of a CMP and dry etch process to remove excess trench filling material above the trench level; and, removing the at least one patterned hardmask layer.
    Type: Application
    Filed: January 29, 2004
    Publication date: August 4, 2005
    Inventors: Chu-Yun Fu, Jhi-Cherng Lu, Syun-Ming Jang
  • Publication number: 20050145614
    Abstract: A semiconductor device manufacturing system including a processing subsystem and a compensation thermal subsystem. The processing subsystem includes a process chamber and a thermal control subsystem having a processing subsystem heating element and configured to generate a process chamber temperature profile. The compensation thermal subsystem includes a temperature sensor configured to detect the process chamber temperature profile, a compensation thermal control unit (CTCU) configured to determine variation between the process chamber temperature profile and a desired temperature profile, and a compensation heating element configured to alter the process chamber temperature profile in response to the variation detected by the CTCU.
    Type: Application
    Filed: January 5, 2004
    Publication date: July 7, 2005
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsueh-Chang Wu, Chih-Tien Chang, Jhi-Cherng Lu, Bing-Hung Chen, Mei-Sheng Zhou
  • Publication number: 20050145937
    Abstract: In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer is formed on the patterned silicon layer. A first layer is formed on the initial structure. Part of the first layer is removed with an etching process, such that a sidewall portion of the patterned silicon layer is exposed and such that a remaining portion of the first layer remains at a corner where the patterned silicon layer interfaces with the buried insulator layer. An oxide liner is formed on the exposed sidewall portion. A recess may be formed in the buried insulator layer (prior to forming the first layer) and may extend partially beneath the patterned silicon layer.
    Type: Application
    Filed: December 29, 2003
    Publication date: July 7, 2005
    Inventors: Kuang-Hsin Chen, Hsun-Chih Tsao, Hung-Wei Chen, Di-Hong Lee, Chuan-Ping Hou, Jhi-Cherng Lu
  • Publication number: 20050110086
    Abstract: A method for forming a field effect transistor includes: forming a conductive region on an isolation layer formed on a substrate, and a cap dielectric layer on the conductive region; forming a sacrificial dielectric layer over the isolation layer and the cap dielectric layer, and on sidewalls of the conductive region; removing a portion of the sacrificial dielectric layer on the cap dielectric layer; removing the cap dielectric layer; removing remaining portions of the sacrificial dielectric layer; forming a gate on the conductive region; and forming source/drain (S/D) regions within the conductive region and adjacent to the gate. A field effect transistor includes a conductive region over an isolation layer formed on a substrate, the conductive region being substantially without undercut at the region within the isolation layer beneath the conductive region; a gate on the conductive region; and S/D regions within the conductive region and adjacent to the gate.
    Type: Application
    Filed: November 24, 2003
    Publication date: May 26, 2005
    Inventors: Chuan-Ping Hou, Jhi-Cherng Lu, Kuang-Hsin Chen, Hsun-Chih Tsao