Patents by Inventor Jhih-Sheng Syu

Jhih-Sheng Syu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Chip and power planning method
    Patent number: 11048850
    Abstract: A chip includes a substrate; macros placed on the substrate, which has a placement region being divided into sub-regions according to locations of the macros; and one or more vertical power stripes (VPSs) disposed in each sub-region. At least one VPS is not aligned with the VPSs of an adjacent higher or lower sub-region.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: June 29, 2021
    Assignees: NCKU Research and Development Foundation, Himax Technologies Limited
    Inventors: Jai-Ming Lin, Jhih-Sheng Syu, Bo-Yuan Huang
  • CHIP AND POWER PLANNING METHOD
    Publication number: 20200074037
    Abstract: A chip includes a substrate; macros placed on the substrate, which has a placement region being divided into sub-regions according to locations of the macros; and one or more vertical power stripes (VPSs) disposed in each sub-region. At least one VPS is not aligned with the VPSs of an adjacent higher or lower sub-region.
    Type: Application
    Filed: November 6, 2019
    Publication date: March 5, 2020
    Inventors: Jai-Ming Lin, Jhih-Sheng Syu, Bo-Yuan Huang
  • Chip and power planning method
    Patent number: 10579765
    Abstract: A chip includes a substrate; macros placed on the substrate, which has a placement region being divided into sub-regions according to locations of the macros; and one or more vertical power stripes (VPSs) disposed in each sub-region. At least one VPS is not aligned with the VPSs of an adjacent higher or lower sub-region.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: March 3, 2020
    Assignees: NCKU Research and Development Foundation, Himax Technologies Limited
    Inventors: Jai-Ming Lin, Jhih-Sheng Syu, Bo-Yuan Huang
  • CHIP AND POWER PLANNING METHOD
    Publication number: 20200034506
    Abstract: A chip includes a substrate; macros placed on the substrate, which has a placement region being divided into sub-regions according to locations of the macros; and one or more vertical power stripes (VPSs) disposed in each sub-region. At least one VPS is not aligned with the VPSs of an adjacent higher or lower sub-region.
    Type: Application
    Filed: July 26, 2018
    Publication date: January 30, 2020
    Inventors: Jai-Ming Lin, Jhih-Sheng Syu, Bo-Yuan Huang