Patents by Inventor Jhih-Wei LAI

Jhih-Wei LAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240088049
    Abstract: A chip packaging structure and a method for fabricating the same are provided. The chip package structure includes a first chip, a second chip, a conductive substrate, a dielectric layer, a vertical conductive structure, a dam and a metal shielding layer. The conductive substrate includes a substrate, vias and electrodes. The vias penetrate through the substrate, and a part of the vias is disposed in a first die-bonding region and a second die-bonding region. The electrodes extend from the first board surface to the second board surface through the vias. The dielectric layer is formed on the substrate to cover a lower electrode portion of each of the electrodes. The vertical conductive structure is formed to be partially embedded into the dielectric layer and provide an electrical path between the first and second die-bonding regions. The dam is formed to surround the first and the second die-bonding regions.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Inventors: DEI-CHENG LIU, JHIH-WEI LAI
  • Publication number: 20240071776
    Abstract: A chip packaging structure and a method for fabricating the same are provided. The chip package structure includes a conductive substrate, a dam and a metal shielding layer. The conductive substrate includes a substrate, vias and electrodes. The substrate has first and second board surfaces opposite to each other. The vias penetrate through the first board surface and the second board surface, and a part of the vias is disposed in a first die-bonding region on which a chip is to be arranged. The electrodes extend from the first board surface to the second board surface through the vias. The dam is formed on the first board surface to surround the first die-bonding region, and the dam has a height higher than that of the chip. The metal shielding layer covers the dam and a part of the first board surface that do not overlap with the electrodes.
    Type: Application
    Filed: December 2, 2022
    Publication date: February 29, 2024
    Inventors: DEI-CHENG LIU, CHIA-SHUAI CHANG, MING-YEN PAN, JIAN-YU SHIH, JHIH-WEI LAI, SHIH-HAN WU
  • Publication number: 20240032204
    Abstract: A method for manufacturing a conductive circuit board includes the steps of: (a) preparing a substrate having opposite upper and lower surfaces, and at least one through hole extending through the upper and lower surfaces and defined by an inner surface; (b) forming a metal base layer on at least one of the upper and lower surfaces and on the inner surface; (c) etching the metal base layer by a laser beam so that the at least one of the upper and lower surfaces and the inner surface are formed with a patterned metal base layer; and (d) forming a metal circuit layer on the at least one of the upper and lower surfaces and on the inner surface to increase a thickness of the patterned metal base layer. A conductive circuit board manufactured therefrom is also enclosed.
    Type: Application
    Filed: September 23, 2022
    Publication date: January 25, 2024
    Inventors: Yueh-Kai TANG, Chia-Shuai CHANG, Ming-Yen PAN, Jian-Yu SHIH, Jhih-Wei LAI, Shih-Han WU