Patents by Inventor Jhih-Yu Wang
Jhih-Yu Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240088056Abstract: A method includes encapsulating a device die in an encapsulating material, forming a first dielectric layer over the device die and the encapsulating material, forming first redistribution lines extending into the first dielectric layer to electrically couple to the device die, forming an alignment mark over the first dielectric layer, wherein the alignment mark includes a plurality of elongated strips, forming a second dielectric layer over the first redistribution lines and the alignment mark, and forming second redistribution lines extending into the second dielectric layer to electrically couple to the first redistribution lines. The second redistribution lines are formed using the alignment mark for alignment.Type: ApplicationFiled: November 15, 2023Publication date: March 14, 2024Inventors: Jhih-Yu Wang, Yung-Chi Chu, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
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Patent number: 11894336Abstract: An integrated fan-out (InFO) package includes a die, a plurality of conductive structures aside the die, an encapsulant laterally encapsulating the die and the conductive structure, and a redistribution structure. The redistribution structure is disposed on the encapsulant. The redistribution structure includes a plurality of routing patterns, a plurality of conductive vias, and a plurality of alignment marks. The routing patterns and the conductive vias are electrically connected to the die and the conductive structures. The alignment marks surround the routing patterns and the conductive vias. The alignment marks are electrically insulated from the die and the conductive structures. At least one of the alignment marks is in physical contact with the encapsulant, and vertical projections of the alignment marks onto the encapsulant have an offset from one another.Type: GrantFiled: September 3, 2021Date of Patent: February 6, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jhih-Yu Wang, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Yung-Chi Chu
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Publication number: 20240038674Abstract: A package includes a die and a redistribution structure. The die has an active surface and is wrapped around by an encapsulant. The redistribution structure disposed on the active surface of the die and located above the encapsulant, wherein the redistribution structure comprises a conductive via connected with the die, a routing pattern located above and connected with the conductive via, and a seal ring structure, the seal ring structure includes a first seal ring element and a second seal ring element located above and connected with the first seal ring element, wherein the second seal ring element includes a seed layer sandwiched between the first seal ring element and the second seal ring element, and a top surface of the first seal ring element is substantially coplanar with a top surface of the conductive via.Type: ApplicationFiled: October 5, 2023Publication date: February 1, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Chi Chu, Hung-Jui Kuo, Jhih-Yu Wang, Yu-Hsiang Hu
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Patent number: 11854997Abstract: A method includes encapsulating a device die in an encapsulating material, forming a first dielectric layer over the device die and the encapsulating material, forming first redistribution lines extending into the first dielectric layer to electrically couple to the device die, forming an alignment mark over the first dielectric layer, wherein the alignment mark includes a plurality of elongated strips, forming a second dielectric layer over the first redistribution lines and the alignment mark, and forming second redistribution lines extending into the second dielectric layer to electrically couple to the first redistribution lines. The second redistribution lines are formed using the alignment mark for alignment.Type: GrantFiled: March 14, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jhih-Yu Wang, Yung-Chi Chu, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
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Patent number: 11798893Abstract: A package includes a die and a redistribution structure. The die has an active surface and is wrapped around by an encapsulant. The redistribution structure disposed on the active surface of the die and located above the encapsulant, wherein the redistribution structure comprises a conductive via connected with the die, a routing pattern located above and connected with the conductive via, and a seal ring structure, the seal ring structure includes a first seal ring element and a second seal ring element located above and connected with the first seal ring element, wherein the second seal ring element includes a seed layer sandwiched between the first seal ring element and the second seal ring element, and a top surface of the first seal ring element is substantially coplanar with a top surface of the conductive via.Type: GrantFiled: March 28, 2022Date of Patent: October 24, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Chi Chu, Hung-Jui Kuo, Jhih-Yu Wang, Yu-Hsiang Hu
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Publication number: 20230290733Abstract: A package structure includes a plurality of semiconductor die, an insulating encapsulant and a redistribution layer. Each of the plurality of semiconductor dies includes a semiconductor substrate, conductive pads disposed on the semiconductor substrate, conductive posts disposed on the conductive pads, and at least one alignment mark located on the semiconductor substrate. The insulating encapsulant is encapsulating the plurality of semiconductor dies. The redistribution layer is disposed on the insulating encapsulant and electrically connected to the plurality of semiconductor dies.Type: ApplicationFiled: May 17, 2023Publication date: September 14, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jhih-Yu Wang, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Yung-Chi Chu
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Patent number: 11694967Abstract: A package structure includes a plurality of semiconductor die, an insulating encapsulant and a redistribution layer. Each of the plurality of semiconductor dies includes a semiconductor substrate, conductive pads disposed on the semiconductor substrate, conductive posts disposed on the conductive pads, and at least one alignment mark located on the semiconductor substrate. The insulating encapsulant is encapsulating the plurality of semiconductor dies. The redistribution layer is disposed on the insulating encapsulant and electrically connected to the plurality of semiconductor dies.Type: GrantFiled: March 14, 2019Date of Patent: July 4, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jhih-Yu Wang, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Yung-Chi Chu
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Publication number: 20220216159Abstract: A package includes a die and a redistribution structure. The die has an active surface and is wrapped around by an encapsulant. The redistribution structure disposed on the active surface of the die and located above the encapsulant, wherein the redistribution structure comprises a conductive via connected with the die, a routing pattern located above and connected with the conductive via, and a seal ring structure, the seal ring structure includes a first seal ring element and a second seal ring element located above and connected with the first seal ring element, wherein the second seal ring element includes a seed layer sandwiched between the first seal ring element and the second seal ring element, and a top surface of the first seal ring element is substantially coplanar with a top surface of the conductive via.Type: ApplicationFiled: March 28, 2022Publication date: July 7, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Chi Chu, Hung-Jui Kuo, Jhih-Yu Wang, Yu-Hsiang Hu
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Publication number: 20220208688Abstract: A method includes encapsulating a device die in an encapsulating material, forming a first dielectric layer over the device die and the encapsulating material, forming first redistribution lines extending into the first dielectric layer to electrically couple to the device die, forming an alignment mark over the first dielectric layer, wherein the alignment mark includes a plurality of elongated strips, forming a second dielectric layer over the first redistribution lines and the alignment mark, and forming second redistribution lines extending into the second dielectric layer to electrically couple to the first redistribution lines. The second redistribution lines are formed using the alignment mark for alignment.Type: ApplicationFiled: March 14, 2022Publication date: June 30, 2022Inventors: Jhih-Yu Wang, Yung-Chi Chu, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
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Patent number: 11289426Abstract: A package includes a die and a redistribution structure. The die has an active surface and is wrapped around by an encapsulant. The redistribution structure disposed on the active surface of the die and located above the encapsulant, wherein the redistribution structure comprises a conductive via connected with the die, a routing pattern located above and connected with the conductive via, and a seal ring structure, the seal ring structure includes a first seal ring element and a second seal ring element located above and connected with the first seal ring element, wherein the second seal ring element includes a seed layer sandwiched between the first seal ring element and the second seal ring element, and a top surface of the first seal ring element is substantially coplanar with a top surface of the conductive via.Type: GrantFiled: June 15, 2018Date of Patent: March 29, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Chi Chu, Hung-Jui Kuo, Jhih-Yu Wang, Yu-Hsiang Hu
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Patent number: 11276647Abstract: A method includes encapsulating a device die in an encapsulating material, forming a first dielectric layer over the device die and the encapsulating material, forming first redistribution lines extending into the first dielectric layer to electrically couple to the device die, forming an alignment mark over the first dielectric layer, wherein the alignment mark includes a plurality of elongated strips, forming a second dielectric layer over the first redistribution lines and the alignment mark, and forming second redistribution lines extending into the second dielectric layer to electrically couple to the first redistribution lines. The second redistribution lines are formed using the alignment mark for alignment.Type: GrantFiled: March 30, 2020Date of Patent: March 15, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jhih-Yu Wang, Yung-Chi Chu, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
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Publication number: 20210398942Abstract: An integrated fan-out (InFO) package includes a die, a plurality of conductive structures aside the die, an encapsulant laterally encapsulating the die and the conductive structure, and a redistribution structure. The redistribution structure is disposed on the encapsulant. The redistribution structure includes a plurality of routing patterns, a plurality of conductive vias, and a plurality of alignment marks. The routing patterns and the conductive vias are electrically connected to the die and the conductive structures. The alignment marks surround the routing patterns and the conductive vias. The alignment marks are electrically insulated from the die and the conductive structures. At least one of the alignment marks is in physical contact with the encapsulant, and vertical projections of the alignment marks onto the encapsulant have an offset from one another.Type: ApplicationFiled: September 3, 2021Publication date: December 23, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jhih-Yu Wang, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Yung-Chi Chu
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Patent number: 11114407Abstract: An integrated fan-out (InFO) package includes an encapsulant, a die, a plurality of conductive structures, and a redistribution structure. The die and the conductive structures are encapsulated by the encapsulant. The conductive structures surround the die. The redistribution structure is disposed on the encapsulant. The redistribution structure includes a plurality of routing patterns, a plurality of conductive vias, and a plurality of alignment marks. The conductive vias interconnects the routing patterns. At least one of the alignment mark is in physical contact with the encapsulant.Type: GrantFiled: June 15, 2018Date of Patent: September 7, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jhih-Yu Wang, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Yung-Chi Chu
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Publication number: 20210125936Abstract: An integrated fan-out (InFO) package includes an encapsulant, a die, a plurality of conductive structures, and a redistribution structure. The die and the conductive structures are encapsulated by the encapsulant. The conductive structures surround the die. The redistribution structure is disposed on the encapsulant. The redistribution structure includes a plurality of routing patterns, a plurality of conductive vias, and a plurality of alignment marks. The conductive vias interconnects the routing patterns. At least one of the alignment mark is in physical contact with the encapsulant.Type: ApplicationFiled: October 29, 2019Publication date: April 29, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jhih-Yu Wang, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
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Patent number: 10978405Abstract: An integrated fan-out (InFO) package includes an encapsulant, a die, a plurality of conductive structures, and a redistribution structure. The die and the conductive structures are encapsulated by the encapsulant. The conductive structures surround the die. The redistribution structure is disposed on the encapsulant. The redistribution structure includes a plurality of routing patterns, a plurality of conductive vias, and a plurality of alignment marks. The conductive vias interconnects the routing patterns. At least one of the alignment mark is in physical contact with the encapsulant.Type: GrantFiled: October 29, 2019Date of Patent: April 13, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jhih-Yu Wang, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
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Publication number: 20200294930Abstract: A package structure includes a plurality of semiconductor die, an insulating encapsulant and a redistribution layer. Each of the plurality of semiconductor dies includes a semiconductor substrate, conductive pads disposed on the semiconductor substrate, conductive posts disposed on the conductive pads, and at least one alignment mark located on the semiconductor substrate. The insulating encapsulant is encapsulating the plurality of semiconductor dies. The redistribution layer is disposed on the insulating encapsulant and electrically connected to the plurality of semiconductor dies.Type: ApplicationFiled: March 14, 2019Publication date: September 17, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jhih-Yu Wang, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Yung-Chi Chu
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Publication number: 20200227357Abstract: A method includes encapsulating a device die in an encapsulating material, forming a first dielectric layer over the device die and the encapsulating material, forming first redistribution lines extending into the first dielectric layer to electrically couple to the device die, forming an alignment mark over the first dielectric layer, wherein the alignment mark includes a plurality of elongated strips, forming a second dielectric layer over the first redistribution lines and the alignment mark, and forming second redistribution lines extending into the second dielectric layer to electrically couple to the first redistribution lines. The second redistribution lines are formed using the alignment mark for alignment.Type: ApplicationFiled: March 30, 2020Publication date: July 16, 2020Inventors: Jhih-Yu Wang, Yung-Chi Chu, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
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Patent number: 10607941Abstract: A method includes encapsulating a device die in an encapsulating material, forming a first dielectric layer over the device die and the encapsulating material, forming first redistribution lines extending into the first dielectric layer to electrically couple to the device die, forming an alignment mark over the first dielectric layer, wherein the alignment mark includes a plurality of elongated strips, forming a second dielectric layer over the first redistribution lines and the alignment mark, and forming second redistribution lines extending into the second dielectric layer to electrically couple to the first redistribution lines. The second redistribution lines are formed using the alignment mark for alignment.Type: GrantFiled: April 30, 2018Date of Patent: March 31, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jhih-Yu Wang, Yung-Chi Chu, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
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Publication number: 20190385951Abstract: A package includes a die and a redistribution structure. The die has an active surface and is wrapped around by an encapsulant. The redistribution structure disposed on the active surface of the die and located above the encapsulant, wherein the redistribution structure comprises a conductive via connected with the die, a routing pattern located above and connected with the conductive via, and a seal ring structure, the seal ring structure includes a first seal ring element and a second seal ring element located above and connected with the first seal ring element, wherein the second seal ring element includes a seed layer sandwiched between the first seal ring element and the second seal ring element, and a top surface of the first seal ring element is substantially coplanar with a top surface of the conductive via.Type: ApplicationFiled: June 15, 2018Publication date: December 19, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yung-Chi Chu, Hung-Jui Kuo, Jhih-Yu Wang, Yu-Hsiang Hu
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Publication number: 20190385975Abstract: An integrated fan-out (InFO) package includes an encapsulant, a die, a plurality of conductive structures, and a redistribution structure. The die and the conductive structures are encapsulated by the encapsulant. The conductive structures surround the die. The redistribution structure is disposed on the encapsulant. The redistribution structure includes a plurality of routing patterns, a plurality of conductive vias, and a plurality of alignment marks. The conductive vias interconnects the routing patterns. At least one of the alignment mark is in physical contact with the encapsulant.Type: ApplicationFiled: June 15, 2018Publication date: December 19, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jhih-Yu Wang, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Yung-Chi Chu