Abstract: A semiconductor device according to the present disclosure includes a first transistor and a second transistor. The first transistor includes first channel members between a first and a second source/drain feature, a first gate structure wrapping around the first channel members, a first source/drain contact disposed over the first source/drain feature, and a first top gate spacer disposed between the first gate structure and the first source/drain contact. The second transistor includes second channel members between a third and a fourth source/drain features, a second gate structure wrapping around the second channel members, a second source/drain contact disposed over the third source/drain feature, and a second top gate spacer disposed between the second gate structure and the second source/drain contact. A distance between the second gate spacer and the second source/drain contact is greater than a distance between the first gate spacer and the first source/drain contact.

Abstract: A semiconductor structure includes a substrate and an array of two-port (TP) SRAM cells. Each TP SRAM cell includes a write port and a read port. The array includes first and second TP SRAM cells. The write ports of the first and second TP SRAM cells abut each other. The write port of the first TP SRAM cell includes a first write pull-down (W_PD) transistor. The write port of the second TP SRAM cell includes a second W_PD transistor. The array of TP SRAM cells further includes a first source/drain contact landing on both a source/drain electrode of the first W_PD transistor and another source/drain electrode of the second W_PD transistor. The first TP SRAM cell includes a first Vss conductor located at a first metal layer. The first Vss conductor is directly above the first source/drain contact and connected to the first source/drain contact.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate having a base, a first fin, and a second fin over the base. The method includes forming a first trench in the base and between the first fin and the second fin. The method includes forming an isolation layer over the base and in the first trench. The first fin and the second fin are partially in the isolation layer. The method includes forming a first gate stack over the first fin and the isolation layer. The method includes forming a second gate stack over the second fin and the isolation layer. The method includes removing a bottom portion of the base. The isolation layer passes through the base after the bottom portion of the base is removed.

Abstract: A method for forming a memory device includes forming a first pull-up transistor, a first pull-down transistor, a first pass-gate transistor, a second pull-up transistor, a second pull-down transistor, a second pass-gate transistor over a substrate; forming a first bit line and a second bit line electrically connected to a source/drain epitaxy structure of the first pass-gate transistor and a source/drain epitaxy structure of the second pass-gate transistor; forming a word line electrically connected to gate structures of the first and second pass-gate transistors; removing the substrate to expose a source/drain epitaxy structure of the first pull-down transistor and a source/drain epitaxy structure of the second pull-down transistor; and forming a first power line electrically connected to the bottom surface of the source/drain epitaxy structure of the first pull-down transistor and electrically connected to the bottom surface of the source/drain epitaxy structure of the second pull-down transistor.

Abstract: A semiconductor device includes first and second active areas, first and second gate structures, and first to third conductive segments. The first and second active areas extend along the first direction. The first and second gate structures cross over the first and second active areas. The first conductive segment crosses over the first and second gate structures, stores a first data signal, and is coupled to the first gate structure, the first and second active areas. The second conductive segment crosses over the first and second gate structures, stores a first complementary data signal, and is coupled to the second gate structure, the first and second active areas. The third conductive segment crosses over the first and second gate structures, and is coupled to the second active area. The first to third conductive segments are arranged in order along a second direction different from the first direction.

Abstract: A method for forming a semiconductor structure is provided. The method for forming the semiconductor structure includes forming a fin structure over a substrate in a first direction, forming a first gate stack, a second gate stack and a third gate stack across the fin structure, removing the first gate stack to form a trench, depositing a cutting structure in the trench, and forming a first contact plug between the cutting structure and the second gate stack and a second contact plug between the second gate stack and the third gate stack. The fin structure is cut into two segments by the trench. A first dimension of the first contact plug in the first direction is greater than a second dimension of the second contact plug in the first direction.

Abstract: A memory device includes a first static random access memory (SRAM) cell, a second SRAM cell, and a first metal layer. The first SRAM cell includes a first write-port pull-up (PU) transistor and a second write-port PU transistor arranged in a Y-direction, and a first read-port PD transistor and a first read-port PG transistor. The second SRAM cell includes a third write-port PU transistor and a fourth write-port PU transistor arranged in the Y-direction, and a second read-port PD transistor and a second read-port PG transistor. The first and second read-port PD transistors and the first and second read-port PG transistors are arranged in the Y-direction. The first metal layer is over the first SRAM cell and the second SRAM cell. The first metal layer includes a read bit-line conductor extending in the Y-direction and shared by the first SRAM cell and the second SRAM cell.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first fin structure disposed at a first device region and extending from a substrate along a first direction, wherein the first fin structure comprises a first recess formed in a top of the first fin structure, the first recess having a bottom and a sidewall extending upwardly from the bottom, wherein the sidewall has a tapering profile. The structure also includes a first source/drain feature in contact with the first fin structure, and a first gate structure disposed in the first recess, the first gate structure extending along a second direction perpendicular to the first direction, wherein the first gate structure has a first gate dielectric layer, and the first gate dielectric layer has a sidewall surface and a bottom surface in contact with the sidewall and the bottom of the first recess, respectively.

Abstract: A semiconductor device including a static random access memory (SRAM) device includes a first SRAM array including a first plurality of bit cells arranged in a matrix; a second SRAM array including a second plurality of bit cells arranged in a matrix; and a plurality of abutting dummy cells disposed between the first SRAM array and the second SRAM array. Each of the plurality of abutting dummy cells includes a plurality of dummy gate electrode layers and a plurality of dummy contacts. The semiconductor device further includes a first-type well continuously extending from the first SRAM array to the second SRAM array. The first-type well is in direct contact with portions of the plurality of dummy contacts.

Abstract: Memory cells are provided. A memory cell includes a first data storage cell, a second data storage cell and a match cell. The first data storage cell includes a first pull-down transistor, a first pull-up transistor and a first pass-gate transistor. The second data storage cell includes a second pull-down transistor, a second pull-up transistor, and a second pass-gate transistor. The match cell includes a first data transistor and a second data transistor. The first data transistor is electrically connected to the first pull-down transistor, the first pull-up transistor and the first pass-gate transistor. The second data transistor is electrically connected to the second pull-down transistor, the second pull-up transistor and the second pass-gate transistor. The first and second data storage cells and the match cell have the same cell height. The match cell is disposed between the first and second data storage cells.

Abstract: A semiconductor structure includes: a substrate; a first fin and a second fin disposed on the substrate and spaced apart from each other; a dielectric wall disposed on the substrate and having first and second wall surfaces; a third fin disposed on the substrate to be in direct contact with at least one of the first and second fins; a first device disposed on the first fin and including first channel features extending away from the first wall surface; a second device disposed on the second fin and including second channel features extending away from the second wall surface; at least one third device disposed on the third fin and including third channel features; and an isolation feature disposed on the substrate to permit the third device to be electrically isolated from the first and second devices. A method for manufacturing the semiconductor structure is also disclosed.

Abstract: A memory device includes a first SRAM cell, a second SRAM cell, a write word line (WWL) landing line, and a Vdd line. The first SRAM cell and the second SRAM cell respectively include 8 transistors. The first WWL landing line is disposed inside a cell boundary of the first SRAM cell. The Vdd line is disposed in a cell boundary of the second SRAM cell. The first WWL landing line and the Vdd line are in a same layer.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of first horizontal nanostructures formed over a substrate, and a plurality of second horizontal nanostructures adjacent to the first horizontal nanostructures. The semiconductor structure includes a dielectric wall formed between the first horizontal nanostructures and the second horizontal nanostructures. The semiconductor structure also includes a vertical nanostructure between the dielectric wall and the first horizontal nanostructures, and the vertical nanostructure is connected to and in direct contact with the dielectric wall. The semiconductor structure includes a gate structure surrounding the first horizontal nanostructures, the second horizontal nanostructures and the vertical nanostructure.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a first stack structure formed over a substrate, and the first stack structure includes a plurality of nanostructures that extend along a first direction. The semiconductor structure includes a second stack structure formed adjacent to the first stack structure, and the second stack structure includes a plurality of nanostructures that extend along the first direction. The semiconductor structure includes a first gate structure formed over the first stack structure, and the first gate structure extends along a second direction. The semiconductor structure also includes a dielectric wall between the first stack structure and the second stack structure, and the dielectric wall includes a low-k dielectric material, and the dielectric wall is connected to the first stack structure and the second stack structure.

Abstract: A semiconductor device includes a substrate, first and second stacks of semiconductor nanosheets, a gate structure, first and second strained layers and first and second dielectric walls. The substrate includes first and second fins. The first and second stacks of semiconductor nanosheets are disposed on the first and second fins respectively. The gate structure wraps the first and second stacks of semiconductor nanosheets. The first and second strained layers are respectively disposed on the first and second fins and abutting the first and second stacks of semiconductor nanosheets. The first dielectric wall is disposed on the substrate and located between the first and second strained layers. The second dielectric wall is disposed on the first dielectric wall and located between the first and second strained layers. A top surface of the second dielectric wall is lower than top surfaces of the first and second strained layers.

Abstract: Fin-based well straps are disclosed for improving performance of memory arrays, such as static random access memory arrays. An exemplary integrated circuit (IC) device includes a FinFET disposed over a doped region of a first type dopant. The FinFET includes a first fin having a first width doped with the first type dopant and first source/drain features of a second type dopant. The IC device further includes a fin-based well strap disposed over the doped region of the first type dopant. The fin-based well strap connects the doped region to a voltage. The fin-based well strap includes a second fin having a second width doped with the first type dopant and second source/drain features of the first type dopant. The second width is greater than the first width. For example, a ratio of the second width to the first width is greater than about 1.1 and less than about 1.5.

Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. The semiconductor structure further includes a gate structure surrounding the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure further includes a contact formed over the source/drain structure and extending into the source/drain structure.

Abstract: A first transistor includes a first gate, a first source/drain, and a first source/drain contact disposed over the first source/drain. The first gate has a first dimension measured in a first lateral direction. The first source/drain contact has a second dimension measured in the first lateral direction. A second transistor includes a second gate, a second source/drain, and a second source/drain contact disposed over the second source/drain. The second gate has a third dimension measured in the first lateral direction. The second source/drain contact has a fourth dimension measured in the first lateral direction. A first ratio of the first dimension and the second dimension is different from a second ratio of the third dimension and the fourth dimension.

Abstract: Semiconductor devices and their manufacturing methods are disclosed herein, and more particularly to semiconductor devices including a transistor having gate all around (GAA) transistor structures and manufacturing methods thereof. Different thickness in an epi-growth scheme is adopted to create different sheet thicknesses within the same device channel regions for use in manufacturing vertically stacked nano structure (e.g., nanosheet, nanowire, or the like) GAA devices. A GAA device may be formed with a vertical stack of nanostructures in a channel region with a topmost nanostructure of the vertical stack being thicker than the other nanostructures of the vertical stack. Furthermore, an LDD portion of the topmost nano structure may be formed as the thickest of the nanostructures in the vertical stack.

Abstract: Semiconductor structures are provided. A semiconductor structure includes a plurality of first logic cells having a first cell height, a plurality of second logic cells having a second cell height, and a plurality of metal lines parallel to each other in a metal layer. The second cell height is different than the first cell height. The first logic cells are arranged in odd rows of a cell array, and the second logic cells are arranged in even rows of the cell array. The metal lines covering the first and second logic cells are wider than the metal lines inside the first logic cells, and the metal lines inside the first logic cells are wider than the metal lines inside the second logic cells.