Patents by Inventor Jhy-Huei Chen

Jhy-Huei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230377965
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate; a gate structure disposed over the substrate and over a channel region of the semiconductor device, wherein the gate structure includes a gate stack and spacers disposed along sidewalls of the gate stack, the gate stack including a gate dielectric layer and a gate electrode; a first metal layer disposed over the gate stack, wherein the first metal layer laterally contacts the spacers over the gate dielectric layer and the gate electrode; and a gate via disposed over the first metal layer.
    Type: Application
    Filed: July 28, 2023
    Publication date: November 23, 2023
    Inventors: Kuo-Chiang Tsai, Jhy-Huei Chen
  • Patent number: 11728216
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate; a gate structure disposed over the substrate and over a channel region of the semiconductor device, wherein the gate structure includes a gate stack and spacers disposed along sidewalls of the gate stack, the gate stack including a gate dielectric layer and a gate electrode; a first metal layer disposed over the gate stack, wherein the first metal layer laterally contacts the spacers over the gate dielectric layer and the gate electrode; and a gate via disposed over the first metal layer.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Chiang Tsai, Jhy-Huei Chen
  • Publication number: 20220157656
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate; a gate structure disposed over the substrate and over a channel region of the semiconductor device, wherein the gate structure includes a gate stack and spacers disposed along sidewalls of the gate stack, the gate stack including a gate dielectric layer and a gate electrode; a first metal layer disposed over the gate stack, wherein the first metal layer laterally contacts the spacers over the gate dielectric layer and the gate electrode; and a gate via disposed over the first metal layer.
    Type: Application
    Filed: January 31, 2022
    Publication date: May 19, 2022
    Inventors: Kuo-Chiang Tsai, Jhy-Huei Chen
  • Patent number: 11239114
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate; a gate structure disposed over the substrate and over a channel region of the semiconductor device, wherein the gate structure includes a gate stack and spacers disposed along sidewalls of the gate stack, the gate stack including a gate dielectric layer and a gate electrode; a first metal layer disposed over the gate stack, wherein the first metal layer laterally contacts the spacers over the gate dielectric layer and the gate electrode; and a gate via disposed over the first metal layer.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: February 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Chiang Tsai, Jhy-Huei Chen
  • Publication number: 20210082756
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate; a gate structure disposed over the substrate and over a channel region of the semiconductor device, wherein the gate structure includes a gate stack and spacers disposed along sidewalls of the gate stack, the gate stack including a gate dielectric layer and a gate electrode; a first metal layer disposed over the gate stack, wherein the first metal layer laterally contacts the spacers over the gate dielectric layer and the gate electrode; and a gate via disposed over the first metal layer.
    Type: Application
    Filed: September 16, 2019
    Publication date: March 18, 2021
    Inventors: Kuo-Chiang Tsai, Jhy-Huei Chen