Patents by Inventor Jhy-Jer Shieh

Jhy-Jer Shieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5804985
    Abstract: The present invention provides an output buffer on a monolithic integrated circuit with programmability, such that one of sixteen output configurations is selected for providing the proper signaling interface to peripheral devices. An input signal (SELECT) in selector circuit (12) provides the transfer of one of two sets of input data signals into function control circuit (14). With the input signal (EN) applied, control signals in the function control circuit (14) set the configuration mode for the output buffer circuit (16). The data input signal INPUT DATA, in accordance with the programmed configuration mode for the output buffer circuit (16), transitions the output signal, DBOUT. The output buffer circuit (16) is programmable for providing an open-drain output, a tri-stated output, a high current output, a low current output, a PCI output, and an output selected from two operating voltages for signal level translation functions.
    Type: Grant
    Filed: April 2, 1996
    Date of Patent: September 8, 1998
    Assignee: Motorola, Inc.
    Inventors: Jhy-Jer Shieh, Dandas Kenneth Tang
  • Patent number: 5751166
    Abstract: A method and a circuit for automatically adjusting a switching threshold of an input buffer circuit (100) to conform to an input signal V.sub.IN which can be from either a TTL or a CMOS logic family. A latch circuit (120) is initialized to set the switching threshold to that of one of the logic families. A level shifting circuit (130) has a switchable load which varies the switching threshold under the control of the latch circuit (120). The amplitude of the input signal V.sub.IN is detected in a threshold detector circuit (110). If the input signal V.sub.IN is a signal from the CMOS logic family, the latch circuit (120) changes state, switching the switchable load of the level shifting circuit (130) to adjust the switching threshold of the input buffer circuit (100).
    Type: Grant
    Filed: June 4, 1996
    Date of Patent: May 12, 1998
    Assignee: Motorola, Inc.
    Inventors: Jhy-Jer Shieh, Dandas K. Tang