Abstract: Disclosed are an anode including a core part and a binder and a secondary battery including the same. Particularly, a coating layer including a polymer is provided between the core part and the binder and thus blocks electron transport paths from the core part to the binder. Thereby, decomposition of the binder is suppressed, and thus, the charge capacity and the initial Coulombic efficiency of the secondary battery are increased.

Abstract: A non-volatile memory includes a memory cell region including an outer region proximate a first end of the memory cell region and an inner region separated from the first end by the outer region, first and second bit lines, an outer memory cell string including memory cells connected to an outer pillar extending vertically upward through the outer region, and an inner memory cell string including memory cells connected to an inner pillar extending vertically upward through the inner region, and a data input/output (I/O). The data I/O circuit includes a page buffer circuit that connects the first bit line during a first read operation directed to memory cells of the outer memory cell string, and connects the second bit line during a second read operation directed to memory cells of the inner memory cell string, and a read voltage determination unit that selects a first optimal read voltage used during the first read operation, and a second optimal read voltage used during the second read operation.

Abstract: An improved switch for an electronic device is provided which includes a main printed circuit board having a contact point mode pattern at an upper surface thereof, and a rotor rotatably installed on the main printed circuit board. One or more brushes are provided with either the rotor or the main printed circuit board so as to be connected to the contact point mode pattern. The rotor may be engaged to a moving member of the electronic device so that the rotor is rotated to different orientations depending on the operational mode of the electronic device. Because the rotor is directly installed on the main printed circuit board, the number of construction components is reduced, and the product can be more compact.

Abstract: A switch for an electronic device includes a main printed circuit board having a contact point mode pattern at an upper surface thereof; and a rotor rotatively installed on the main printed circuit board with one or more brushes mounted therein so as to be connected to the contact point mode pattern. The rotor may be engaged to a moving member of the electronic device so that the rotor is rotated to different orientations depending on the operational mode of the electronic device. Because the rotor is directly installed on the main printed circuit board, the number of construction components is reduced, and the product can be more compact.

Abstract: A refresh control circuit is provided that includes a control signal latency setting circuit that sets a control signal (CAS) latency, and a refresh mode setting that receives an output signal (REF) from the auto refresh mode decoder and an output signal (SREF) from the self-refresh mode decoder and outputs an output signal.

Abstract: A memory module having a module control circuit which is capable of decreasing an operational current by configuring a 1BANK 4M.times.64 module using 16M DRAMs (1K Refresh.times.16) and reducing the number of operational devices. The module control circuit decodes externally inputted eleventh and twelfth address signals and outputs control signals in accordance with one of a plurality of column address strobe signals and a row address strobe signal, and a plurality of DRAMs in a memory unit are selected by the control signals from the module control circuit and are parallely connected for performing a data write and read operation in accordance with externally inputted first through tenth address signals, a write enable signal, an output enable signal, and the column address strobe signals.

Abstract: A refresh method of reusing electric charges from a refresh operation of a first memory array for pre-charging in an initial refresh operation of a second memory array in which charges that are charged/discharged to a bit line and its complementary bit line of one memory array via switching units provided between the one memory array and another memory array when performing a refresh operation in the one memory array are also used for performing an initial refresh operation of the other memory array, thereby reducing back-up currents by reducing refresh currents, and prolonging the life of dry cells or batteries for hours.