Abstract: An integrated circuit includes a first standard cell including a first first-type transistor, a first second-type transistor, a third second-type transistor, and a third first-type transistor, a second standard cell including a second first-type transistor, a second second-type transistor, a fourth second-type transistor and a fourth first-type transistor, a plurality of wiring layers which are disposed on the first and second standard cells and includes a first wiring layer, a second wiring layer, and a third wiring layer sequentially stacked. A source contact of the first first-type transistor and a source contact of the second first-type transistor are electrically connected through a first power rail of the plurality of wiring layers, and a source contact of the third first-type transistor and a source contact of the fourth first-type transistor are electrically connected through a second power rail of the plurality of wiring layers.

Abstract: A secure booting apparatus according to an embodiment for solving the problems to be solved by the present invention includes: a memory configured to store encrypted data, an encrypted header, and a symmetric key; and a processor configured to generate decrypted data and a decrypted header by applying a symmetric key algorithm using the symmetric key to the encrypted data and encrypted header, to include a public key and a pre key generated from the public key in the decrypted header, to generate a comparison hashed message by applying a hash algorithm to the decrypted data, to generate a final verification value by applying a public key algorithm using the public key and the pre key to the decrypted header, to compare the comparison hashed message with the final verification value, and to determine that booting has failed if the comparison hashed message and the final verification value are different from each other.

Abstract: A brush includes a roller body, a first brush layer and a second brush layer. The first brush layer covers an outer surface of the roller body. The second brush layer is on the first brush layer, and is thinner than the first brush layer. The rate of pore formation of the second layer is lower than the rate of pore formation of the first brush layer.

Abstract: Provided herein are chemical mechanical polishing (CMP) slurries and methods for producing the same. Embodiments of the invention include CMP slurries that include (a) a metal oxide; (b) a quaternary ammonium base; and (c) a fluorinated surfactant. In some embodiments, the fluorinated surfactant is a non-ionic perfluoroalkyl sulfonyl compound. Also provided herein are methods of polishing a polycrystalline silicon surface, including providing a slurry composition according to an embodiment of the invention to a polycrystalline silicon surface and performing a CMP process to polish the polycrystalline silicon surface.