Abstract: Disclosed herein is a gate driver which is capable of partially driving a screen. The gate driver includes a first shift register for sequentially outputting n scan pulses (where n is a natural number larger than 2), and a second shift register for selecting p ones (where p is a natural number smaller than or equal to n) of the n scan pulses from the first shift register in response to an external output control signal and supplying the selected p scan pulses respectively to p gate lines of a liquid crystal panel.

Abstract: A shift register is disclosed.

Abstract: A shift register which is capable of simultaneously driving gate lines is disclosed. The shift register includes a plurality of stages for simultaneously supplying all-drive signals to gate lines for an all-drive period and sequentially supplying scan pulses to the gate lines for a scan period.

Abstract: Disclosed in an electrophoretic display device having a charged ink layer. In this disclosed device, the ink layer is disposed on the active region (an image display region) and the peripheral region located around the active region, and an electric field is applied to a portion of the electrophoretic ink film corresponding to the peripheral region. Therefore, the peripheral region does not look stained.

Abstract: An apparatus and method for driving a liquid crystal display device are disclosed. The apparatus includes a liquid crystal panel with pixels defined by data and gate lines. A gate driver provides different gate pulses to the odd-column pixels than to the even-column pixels. The gate pulses have different voltages and/or widths. Data drivers provide data voltages having a positive or negative polarity to the data lines. A timing controller controls the gate and data drivers and supplies gate clock pulses that have different voltages and/or widths to the gate driver.

Abstract: An apparatus and method for driving a liquid crystal display device are disclosed. The apparatus includes a liquid crystal panel with pixels defined by data and gate lines. A gate driver provides different gate pulses to the odd-column pixels than to the even-column pixels. The gate pulses have different voltages and/or widths. Data drivers provide data voltages having a positive or negative polarity to the data lines. A timing controller controls the gate and data drivers and supplies gate clock pulses that have different voltages and/or widths to the gate driver.

Abstract: Disclosed in an electrophoretic display device having a charged ink layer. In this disclosed device, the ink layer is disposed on the active region (an image display region) and the peripheral region located around the active region, and an electric field is applied to a portion of the electrophoretic ink film corresponding to the peripheral region. Therefore, the peripheral region does not look stained.

Abstract: A shift register minimizing bias stress applied to transistors is disclosed.

Abstract: A liquid crystal display device including a liquid crystal panel, a gate driver configured to supply gate signals to gate lines on the liquid crystal panel, a data driver configured to supply data voltages to data lines on the liquid crystal panel, and a partial controller configured to control the gate driver to intercept a part of the gate signals to be supplied to the gate lines.

Abstract: A gate driving circuit for a liquid crystal display device includes a plurality of shift register stages each including pull-up and pull-down transistors, wherein each of the pull-up and pull-down transistors is connected to a gate driving signal output terminal and controlled by voltages on first and second nodes, respectively, and wherein the pull-down transistors of a (2n?1)th shift register stage and a (2n)th shift register stage are connected to each other; and a control signal generating unit alternately supplying one of first and second control signals to the pull-down transistors of the (2n?1)th and (2n)th shift register stages and supplying the other of the first and second control signals to the pull-down transistors of the (2n+1)th and (2n+2)th shift register stages, wherein n is an positive integer.