Abstract: A sensing block includes a block body having a plurality of slots through which electrode leads of battery cells pass, a plurality of sensing terminals installed between the plurality of slots on a front surface of the block body, a circuit board installed on the front surface of the block body, and a connector installed on the circuit board.

Abstract: A battery cell cartridge in which a battery cell is accommodated, includes first, second, third and fourth frames formed in a quadrangular shape, wherein the first frame and the second frame extend along a horizontal direction and are spaced from each other at a predetermined interval therebetween, the first frame is positioned on an upper side and the second frame is positioned on a lower side, the third frame and the fourth frame extend along a vertical direction and are spaced from each other at a predetermined interval therebetween, and the third frame is positioned on a first side and the third frame is positioned on a second side opposite to the second frame.

Abstract: The present invention relates to an allulose storage package for increasing storage stability of allulose syrup and a method for increasing the storage stability of allulose.

Abstract: The present invention relates to a dextrin with improved turbidity, and a method for producing same.

Abstract: The present disclosure relates to an apparatus for trapping of a reaction by-product with an extended available collection area. The configuration of the present disclosure relates to an apparatus for trapping of a reaction by-product, which is configured to accommodate gas, which is discharged after a deposition process during a semiconductor manufacturing process, in a housing (1), heat the gas with a heater (2), trap a reaction by-product contained in the gas by using an internal trapping tower (3), and discharge only the gas.

Abstract: The present disclosure relates to an apparatus for trapping of a reaction by-product with an extended available collection area. The configuration of the present disclosure relates to an apparatus for trapping of a reaction by-product, which is configured to accommodate gas, which is discharged after a deposition process during a semiconductor manufacturing process, in a housing (1), heat the gas with a heater (2), trap a reaction by-product contained in the gas by using an internal trapping tower (3), and discharge only the gas.

Abstract: The present disclosure relates to an apparatus for trapping a reaction by-product created by an etching process, the apparatus being configured to trap a reaction by-product contained in an unreacted gas discharged after a process is performed in an etching process chamber during a semiconductor manufacturing process, trap and stack the reaction by-product in the form of powder at a position between a vacuum pump and a scrubber through multiple flow path switching structures, multiple trapping structures, and multiple stacking structures, and discharge only a gaseous unreacted gas to the scrubber.

Abstract: An apparatus is for trapping multiple reaction by-products for a semiconductor process, in which a trapping region is divided by a difference in vertical temperature distribution according to a distance spaced apart from a heater and by structures for switching flow path directions and generating multiple vortices using a trapping structure, and reaction by-product mixtures contained in a gas, which is discharged after a process of depositing multiple different thin film layers is performed in a process chamber during a semiconductor manufacturing process, is trapped by a single trapping apparatus, such that a reaction by-product, which is aggregated in the form of a thin film in a relatively high-temperature region, is trapped by a first trapping part in an upper region, and a reaction by-product, which is aggregated in the form of powder in a relatively low-temperature region, is trapped by a second trapping part in a lower region.

Abstract: The present disclosure relates to an apparatus for trapping multiple reaction by-products for a semiconductor process, in which in order to separate, with the single trapping apparatus, reaction by-product mixtures contained in unreacted gases discharged after a process of depositing multiple different thin film layers is performed in a process chamber during a semiconductor manufacturing process, a trapping region division part is provided, which divides a heat distribution region into trapping regions for respective reaction by-products while controlling a flow in a movement direction of an introduced unreacted gas, thereby trapping a reaction by-product aggregated in the form of a thin film in a relatively high-temperature region by using a first internal trapping tower in a front region, and trapping a reaction by-product aggregated in the form of powder in a relatively low-temperature region by using a second internal trapping tower in a rear region.

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

Abstract: A method includes forming a first etch target layer and a first mask layer on a substrate. Sacrificial patterns extending in a first direction are formed on the first mask layer in a second direction. Spacers are formed on sidewalls of the sacrificial patterns. After removing the sacrificial patterns, the first mask layer is etched using the spacers as an etching mask to form first masks. Second masks are formed on sidewalls of each first mask to define a third masks including each first mask and the second masks on sidewalls of each first mask. The first etch target layer is etched using the first and third masks as an etching mask to form first and second patterns in the first and second regions, respectively. Each first pattern has a first width, and each second pattern has a second width greater than the first width.

Abstract: The present invention relates to a soluble polypeptide comprised of repeat modules. More particularly, the present invention relates to a soluble fusion polypeptide of the N-terminal domain of internalin and LRR (Leucine rich repeat) family protein, a method for preparing the polypeptide, a vector comprising a nucleic acid sequence encoding the polypeptide, a host cell comprising the vector, a method for producing a solubility and folding-improved fusion polypeptide by expressing the vector in the host cell, and a method for improving the solubility and folding of the fusion polypeptide. Further, the present invention relates to a method for preparing the polypeptide bound with a specific target and analyzing the efficacy of the soluble polypeptide.

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

Abstract: A method includes forming a first etch target layer and a first mask layer on a substrate. Sacrificial patterns extending in a first direction are formed on the first mask layer in a second direction. Spacers are formed on sidewalls of the sacrificial patterns. After removing the sacrificial patterns, the first mask layer is etched using the spacers as an etching mask to form first masks. Second masks are formed on sidewalls of each first mask to define a third masks including each first mask and the second masks on sidewalls of each first mask. The first etch target layer is etched using the first and third masks as an etching mask to form first and second patterns in the first and second regions, respectively. Each first pattern has a first width, and each second pattern has a second width greater than the first width.

Abstract: The disclosure provides semiconductor devices and methods of manufacturing the same. The method includes etching a substrate using a first mask pattern formed on the substrate to form a trench, forming a preliminary device isolation pattern filling the trench and including first and second regions having first thicknesses, forming a second mask pattern on the first region, etching an upper portion of the second region and a portion of the first mask pattern, which are exposed by the second mask pattern, to form a second region having a second thickness smaller than the first thickness, removing the first and second mask patterns, and etching upper portions of the first region and the second region having the second thickness to form a device isolation pattern defining preliminary fin-type active patterns. An electronic device including a semiconductor device and a manufacturing method thereof are also disclosed.

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

Abstract: The disclosure provides semiconductor devices and methods of manufacturing the same. The method includes etching a substrate using a first mask pattern formed on the substrate to form a trench, forming a preliminary device isolation pattern filling the trench and including first and second regions having first thicknesses, forming a second mask pattern on the first region, etching an upper portion of the second region and a portion of the first mask pattern, which are exposed by the second mask pattern, to form a second region having a second thickness smaller than the first thickness, removing the first and second mask patterns, and etching upper portions of the first region and the second region having the second thickness to form a device isolation pattern defining preliminary fin-type active patterns. An electronic device including a semiconductor device and a manufacturing method thereof are also disclosed.

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.