Patents by Inventor Ji-Eun Lim

Ji-Eun Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145719
    Abstract: A binder solution for an all-solid-state battery, an electrode slurry for an all-solid-state battery including the same and a method of manufacturing an all-solid-state battery using the same, and more particularly to a binder solution for an all-solid-state battery, in which a polymer binder configured such that a non-polar functional group is bonded to the end of a polar functional group is used, whereby the polar functional group is provided by a deprotection mechanism of the polymer binder through a thermal treatment, thus increasing adhesion between electrode materials to thereby improve battery capacity and enabling a wet process to thereby reduce manufacturing costs, an electrode slurry for an all-solid-state battery including the same and a method of manufacturing an all-solid-state battery using the same.
    Type: Application
    Filed: January 10, 2024
    Publication date: May 2, 2024
    Applicants: HYUNDAI MOTOR COMPANY, Kia Corporation, Seoul National University R&DB Foundation
    Inventors: Sang Mo Kim, Sang Heon Lee, Yong Sub Yoon, Jae Min Lim, Ju Yeong Seong, Jin Soo Kim, Jang Wook Choi, Kyu Lin Lee, Ji Eun Lee
  • Patent number: 11825022
    Abstract: Disclosed is an AI avatar coaching system based on a free speech emotion analysis for acting for CS managers.
    Type: Grant
    Filed: October 27, 2022
    Date of Patent: November 21, 2023
    Assignee: CS Sharing Inc.
    Inventor: Ji Eun Lim
  • Patent number: 9650238
    Abstract: A vibration device including a supporting portion formed to cover both ends of a vibration region, and a method of manufacturing the vibration device are provided. The vibration device may include a lower substrate on which an insulating layer is formed, an upper substrate connected onto the insulating layer, and including a vibration region that vibrates and that is separated from the lower substrate by at least a predetermined distance, and a supporting portion formed to cover both ends of the vibration region, to support the vibration region.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: May 16, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: In Bok Baek, Han Young Yu, Yark Yeon Kim, Young Jun Kim, Chang Geun Ahn, Yong Sun Yoon, Bong Kuk Lee, Ji Eun Lim, Won Ick Jang
  • Patent number: 9153499
    Abstract: Provided is a semiconductor device including first, second and third source/drain regions. A first conductive plug in contact with the first source/drain regions, having a first width and a first height, and including a first material is provided. An interlayer insulating layer covering the first conductive plug and the substrate is disposed. A second conductive plug vertically penetrating the interlayer insulating layer to be in contact with the second source/drain regions, having a second width and a second height, and including a second material is provided. A third conductive plug vertically penetrating the interlayer insulating layer to be in contact with the third source/drain regions, having a third width and a third height, and including a third material is disposed. The second material includes a noble metal, a noble metal oxide or a perovskite-based conductive oxide.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: October 6, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wan-Don Kim, Seung-Hwan Lee, Beom-Seok Kim, Kyu-Ho Cho, Oh-Seong Kwon, Geun-Kyu Choi, Ji-Eun Lim, Yong-Suk Tak
  • Publication number: 20150061455
    Abstract: A vibration device including a supporting portion formed to cover both ends of a vibration region, and a method of manufacturing the vibration device are provided. The vibration device may include a lower substrate on which an insulating layer is formed, an upper substrate connected onto the insulating layer, and including a vibration region that vibrates and that is separated from the lower substrate by at least a predetermined distance, and a supporting portion formed to cover both ends of the vibration region, to support the vibration region.
    Type: Application
    Filed: September 2, 2014
    Publication date: March 5, 2015
    Inventors: In Bok BAEK, Han Young YU, Yark Yeon KIM, Young Jun KIM, Chang Geun AHN, Yong Sun YOON, Bong Kuk LEE, Ji Eun LIM, Won Ick JANG
  • Publication number: 20140231951
    Abstract: Provided is a structure of a silicon photomultiplier including an insulating layer to isolate pixels in the silicon photomultiplier and a quench resistor formed on the insulating layer to maximize the size of a light-receiving area, and a method of manufacturing the silicon photomultiplier.
    Type: Application
    Filed: February 14, 2014
    Publication date: August 21, 2014
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Yong Sun YOON, Ji Eun LIM, Han Young YU, Won Ick JANG
  • Publication number: 20140050621
    Abstract: Provided are a biosensor and a biomaterial detection apparatus including the same. The biomaterial detection apparatus comprises a light source to provide quantized photons; a substrate spaced apart from the light source; a single photonic sensor layer disposed on the substrate to sense the photons; and an adsorption layer disposed to cover the single photonic sensor layer, allow the photons to pass therethrough, and adsorb a biomaterial between the light source and the substrate.
    Type: Application
    Filed: June 14, 2013
    Publication date: February 20, 2014
    Inventors: Han Young YU, Yong Sun YOON, Yark Yeon KIM, Won Ick JANG, Eun-ju JEONG, Ji Eun LIM
  • Publication number: 20120299072
    Abstract: Provided is a semiconductor device including first, second and third source/drain regions. A first conductive plug in contact with the first source/drain regions, having a first width and a first height, and including a first material is provided. An interlayer insulating layer covering the first conductive plug and the substrate is disposed. A second conductive plug vertically penetrating the interlayer insulating layer to be in contact with the second source/drain regions, having a second width and a second height, and including a second material is provided. A third conductive plug vertically penetrating the interlayer insulating layer to be in contact with the third source/drain regions, having a third width and a third height, and including a third material is disposed. The second material includes a noble metal, a noble metal oxide or a perovskite-based conductive oxide.
    Type: Application
    Filed: March 21, 2012
    Publication date: November 29, 2012
    Inventors: WAN-DON KIM, Seung-Hwan Lee, Beom-Seok Kim, Kyu-Ho Cho, Oh-Seong Kwon, Geun-Kyu Choi, Ji-Eun Lim, Yong-Suk Tak
  • Patent number: 7867880
    Abstract: The present invention provides metal precursors for low temperature deposition. The metal precursors include a metal ring compound including at least one metal as one of a plurality of elements forming a ring. Methods of forming a metal thin layer and manufacturing a phase change memory device including use of the metal precursors is also provided.
    Type: Grant
    Filed: July 2, 2007
    Date of Patent: January 11, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hye-young Park, Sung-lae Cho, Byoung-jae Bae, Jin-il Lee, Ji-eun Lim, Young-lim Park
  • Patent number: 7759667
    Abstract: A phase change memory device includes a lower electrode provided on a substrate, an interlayer insulating layer including a contact hole exposing the lower electrode, and covering the substrate, a resistant material pattern filling the contact hole, a phase change pattern interposed between the resistant material pattern and the interlayer insulating layer, and extending between the resistant material pattern and the lower electrode, wherein the resistant material pattern has a higher resistance than the phase change pattern, and an upper electrode in contact with the phase change pattern, the upper electrode being electrically connected to the lower electrode through the phase change pattern.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: July 20, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Lim Park, Sung-Lae Cho, Byoung-Jae Bae, Jin-il Lee, Hye-Young Park, Ji-Eun Lim
  • Patent number: 7727884
    Abstract: A method includes forming a phase change material layer on a substrate using a deposition process that employs a process gas. The process gas includes a germanium source gas, and the germanium source gas includes at least one of the atomic groups “—N?C?O”, “—N?C?S”, “—N?C?Se”, “—N?C?Te”, “—N?C?Po” and “—C?N”.
    Type: Grant
    Filed: July 19, 2007
    Date of Patent: June 1, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoung-Jae Bae, Sung-Lae Cho, Jin-Il Lee, Hye-Young Park, Ji-Eun Lim, Young-Lim Park
  • Patent number: 7583095
    Abstract: A probe array may be fabricated by forming probes arranged on a sacrificial substrate, forming a probe substrate above the probes, and removing the sacrificial substrate. In one embodiment, first probes may be two-dimensionally formed in row and column directions on a sacrificial substrate. Second probes may be formed between the first probes arranged in the row direction such that a distance between the first and second probes is smaller than the resolution limit in a lithography process. A probe substrate may be formed on the sacrificial substrate having the first and second probes, and the sacrificial substrate may be removed.
    Type: Grant
    Filed: August 15, 2006
    Date of Patent: September 1, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Chul Yoo, Byoung-Jae Bae, Jang-Eun Heo, Ji-Eun Lim, Dong-Hyun Im
  • Publication number: 20080142777
    Abstract: A phase change memory device includes a lower electrode provided on a substrate, an interlayer insulating layer including a contact hole exposing the lower electrode, and covering the substrate, a resistant material pattern filling the contact hole, a phase change pattern interposed between the resistant material pattern and the interlayer insulating layer, and extending between the resistant material pattern and the lower electrode, wherein the resistant material pattern has a higher resistance than the phase change pattern, and an upper electrode in contact with the phase change pattern, the upper electrode being electrically connected to the lower electrode through the phase change pattern.
    Type: Application
    Filed: June 14, 2007
    Publication date: June 19, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Lim PARK, Sung-Lae CHO, Byoung-Jae BAE, Jin-Il LEE, Hye-Young PARK, Ji-Eun LIM
  • Publication number: 20080108174
    Abstract: The present invention provides metal precursors for low temperature deposition. The metal precursors include a metal ring compound including at least one metal as one of a plurality of elements forming a ring. Methods of forming a metal thin layer and manufacturing a phase change memory device including use of the metal precursors is also provided.
    Type: Application
    Filed: July 2, 2007
    Publication date: May 8, 2008
    Inventors: Hye-young Park, Sung-Iae Cho, Byoung-jae Bae, Jin-il Lee, Ji-eun Lim, Young-lim Park
  • Publication number: 20080096386
    Abstract: A phase-changeable layer and a method of forming the same are disclosed. In the method, a first hydrogen gas is introduced into a reaction chamber into which a substrate is loaded at a first flow rate to form first plasma. A primary cyclic CVD process is carried out using precursors in the reaction chamber to form a lower phase-changeable layer having a first grain size on the substrate. A second hydrogen gas is introduced into the reaction chamber at a second flow rate less than the first flow rate to form second plasma. A secondary cyclic CVD process is carried out using the precursors in the reaction chamber to form an upper phase-changeable layer having a second grain size smaller than the first grain size on the substrate, thereby forming a phase-changeable layer. Thus, the phase-changeable layer may have strong adhesion strength with respect to a lower layer and good electrical characteristics.
    Type: Application
    Filed: October 22, 2007
    Publication date: April 24, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Lim PARK, Sung-Lae CHO, Byoung-Jae BAE, Jin-Il LEE, Hye-Young PARK, Ji-Eun LIM
  • Publication number: 20080054244
    Abstract: In one embodiment, a phase change memory device includes an insulation structure over a substrate. The insulation structure ahs an opening defined therethrough. A first layer pattern is formed on sidewalls and a bottom of the opening. A second layer pattern is formed on the first layer pattern and substantially fills the opening.
    Type: Application
    Filed: April 5, 2007
    Publication date: March 6, 2008
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jin-Il Lee, Ji-Eun Lim, Hye-Young Park, Sung-Lae Cho, Eun-Ae Chung, Ki-Vin Im, Byoung-Jae Bae, Young-Lim Park
  • Publication number: 20080020564
    Abstract: A method includes forming a phase change material layer on a substrate using a deposition process that employs a process gas. The process gas includes a germanium source gas, and the germanium source gas includes at least one of the atomic groups “—N?C?O”, “—N?C?S”, “—N?C?Se”, “—N?C?Te”, “—N?C?Po” and “—C?N”.
    Type: Application
    Filed: July 19, 2007
    Publication date: January 24, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byoung-Jae BAE, Sung-Lae CHO, Jin-Il LEE, Hye-Young PARK, Ji-Eun LIM, Young-Lim PARK
  • Publication number: 20070210812
    Abstract: A probe array may be fabricated by forming probes arranged on a sacrificial substrate, forming a probe substrate above the probes, and removing the sacrificial substrate. In one embodiment, first probes may be two-dimensionally formed in row and column directions on a sacrificial substrate. Second probes may be formed between the first probes arranged in the row direction such that a distance between the first and second probes is smaller than the resolution limit in a lithography process. A probe substrate may be formed on the sacrificial substrate having the first and second probes, and the sacrificial substrate may be removed.
    Type: Application
    Filed: August 15, 2006
    Publication date: September 13, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Chul YOO, Byoung-Jae BAE, Jang-Eun HEO, Ji-Eun LIM, Dong-Hyun IM
  • Publication number: 20070058415
    Abstract: Disclosed are methods of forming ferroelectric material layers introducing a plurality of metallorganic source compounds into the reaction chamber, the source compounds being supplied in an appropriate ratio for forming the ferroelectric material. These metallorganic source compounds are, in turn, reacted with a NyOx/O2 oxidant gas mixture in which the NyOxcomponent(s) represents at least 50 volume percent of the oxidant gas. This mixture of metallorganic source compounds and oxidant gas mixture(s) are maintained at a deposition temperature and deposition pressure within the reaction chamber suitable for causing a reaction between the metallorganic source compounds and the oxidant gas for a deposition period sufficient to form the ferroelectric material layer. The resulting ferroelectric material layers exhibit improved uniformity, for example, near the interface with the bottom electrode.
    Type: Application
    Filed: September 14, 2006
    Publication date: March 15, 2007
    Inventors: Dong-Hyun Im, Byoung-Jae Bae, Ji-Eun Lim, Dong-Chul Yoo, Yeon-Kyu Jung
  • Publication number: 20070045689
    Abstract: In a ferroelectric structure after a first lower electrode film is formed using a first metal nitride, a second lower electrode film is formed on the first lower electrode film using a first metal, a second metal oxide and/or a first alloy. After a ferroelectric layer is formed on the second lower electrode film, a first upper electrode film is formed on the ferroelectric layer using a second alloy. Related devices are also disclosed.
    Type: Application
    Filed: July 26, 2006
    Publication date: March 1, 2007
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ji-Eun Lim, Dong-Chul Yoo, Byoung-Jae Bae, Dong-Hyun Im, Suk-Pil Kim