Abstract: A method of manufacturing a multilayer electronic component, the method includes, attaching a margin portion green sheet including a ceramic material, a photocuring agent, and a photoinitiator to at least one end surface of each of the plurality of cut ceramic green sheet stacked bodies in the third direction, an energy irradiation operation of irradiating, with energy, the margin portion green sheet to generate a photocuring polymerization reaction between the photocuring agent and the photoinitiator.

Abstract: Disclosed are wood preforming devices for manufacturing a crash pad for a vehicle including a real wood sheet. A wood preforming device for manufacturing a crash pad for a vehicle includes a real wood sheet includes a lower press mold comprising a debossed portion provided on a portion on which a product is formed, and a support portion configured to support an upper press mold, in response to the lower press mold and the upper press mold pressing each other, the support portion having a protrusion for fixing a real wood sheet, the upper press mold having an embossed portion corresponding to the debossed portion of the lower press mold, and a movable core provided on the debossed portion of the lower press mold and being configured to guide the real wood sheet by moving upward from the debossed portion, in response to the upper press mold moving downward.

Abstract: Provided is a galvannealed steel sheet having excellent powdering resistance, and a manufacturing method therefor. The galvannealed steel sheet includes: base iron; and an alloying hot-dip galvanized layer provided on the surface thereof. The base iron includes, by weight %; 0.003 to 0.009% of carbon (C); 0.05% or less of silicon (Si); 0.4 to 1.0% of manganese (Mn); 0.04 to 0.09% of phosphorus (P); 0.01% or less of sulfur (S); 0.005% or less of nitrogen (N); 0.1% or less of aluminum (S.Al); 0.05 to 0.08% of molybdenum (Mo); 0.005 to 0.03% of titanium (Ti); 0.02 to 0.045% of niobium (Nb); 0.06 to 0.1% of copper (Cu); 0.0015% or less of boron (B), and a balance of Fe and inevitable impurities. An average thickness of a gamma (?) phase present at an interface between the base iron and the alloying hot-dip galvanized layer is 0.20 ?m or less.

Abstract: Provided is a lamp for a vehicle to prevent light efficiency from being deteriorated while being embodied in a slim form factor. The lamp for a vehicle includes a light emission portion to generate light; a first optical portion disposed in front of the light emission portion to allow the light generated from the light emission portion to be incident thereto; and a second optical portion disposed between the light emission portion and the first optical portion. The second optical portion refracts the light in a direction different from a light refracting direction of the first optical portion.

Abstract: Disclosed are: a fusion polypeptide comprising growth differentiation factor 15 (GDF15) and a polypeptide region capable of O-glycosylation; a pharmaceutical composition comprising the fusion polypeptide; and a method for increasing the in vivo duration of GDF15, comprising the step of fusing a polypeptide region capable of O-glycosylation.

Abstract: Provided is a fusion polypeptide comprising GDF15 (Growth/differentiation factor 15) and an Fc region of immunoglobulin, a pharmaceutical composition comprising the fusion polypeptide, and a method of increasing in vivo duration of GDF15 comprising fusing with an Fc region of immunoglobulin.

Abstract: The present invention relates to a compound exhibiting excellent agonist activity against melanocortin receptors. More specifically, the present invention relates to a compound of Formula 1, a pharmaceutical composition comprising the compound as an active ingredient, and a use thereof, and the compound of the present invention exhibits excellent agonist activity against melacortin-4 receptors and can be particularly useful in preventing or treating obesity, diabetes, inflammation and erectile dysfunction.

Abstract: Provided is a lamp for a vehicle to prevent light efficiency from being deteriorated while being embodied in a slim form factor. The lamp for a vehicle includes a light emission portion to generate light; a first optical portion disposed in front of the light emission portion to allow the light generated from the light emission portion to be incident thereto; and a second optical portion disposed between the light emission portion and the first optical portion. The second optical portion refracts the light in a direction different from a light refracting direction of the first optical portion.

Abstract: A method of forming an isolation layer in a semiconductor device is disclosed, by which breakdown voltage and PN junction leakage characteristics of the isolation layer are enhanced. Embodiments include depositing a pad nitride layer over a semiconductor substrate, reducing the thickness of the pad nitride layer by etching a portion of the pad nitride layer, forming a tetraethyl orthosilicate (TEOS) oxide layer over the remaining pad nitride layer, forming a trench by selectively removing the tetraethyl orthosilicate oxide layer and the pad nitride layer over an isolation area of the semiconductor substrate, depositing an high density plasma oxide layer over the substrate to fill the trench, and forming an isolation layer by planarizing the high density plasma oxide layer and the tetraethyl orthosilicate oxide layer.

Abstract: Provided are semiconductor devices and methods of fabricating the same. The semiconductor device comprises: a floating gate pattern formed in a cell area of a semiconductor substrate; a dummy floating gate pattern extending from the floating gate pattern into an interface area around the cell area; and a control gate pattern intersecting the floating gate pattern at the cell area of the semiconductor substrate.

Abstract: An image sensor and method of manufacturing the same are provided. According to an embodiment, the image sensor comprises: a circuit including an interconnection on a substrate; a lower electrode on the interconnection; a separated intrinsic layer on the lower electrode; a second conductive type conduction layer on the separated intrinsic layer; and an upper electrode on the second conductive type conduction layer. The separated intrinsic layer can have an inwardly sloping sidewall to focus light incident the photodiode for the unit pixel.

Abstract: Provided is a monitoring pattern for a silicide that may include a plurality of poly pads, a plurality of N-well regions and P-well regions, active regions, and a poly gate line. The plurality of poly pads are disposed on a semiconductor substrate. The plurality of N-well regions and P-well regions are disposed in a single line between the poly pads. The active regions are disposed on the N-well and the P-well regions. The poly gate line electrically connects the active regions to the poly pads and has a configuration permitting it to pass through the active regions a plurality of times.

Abstract: Disclosed is a method of manufacturing a semiconductor device. The method comprises consecutively depositing and patterning polysilicon and mask material on a substrate to form a polysilicon layer and a mask layer, reducing a width of the polysilicon layer, depositing and etching insulating material on the substrate to form a spacer on a lateral side of the polysilicon layer, and forming a source/drain region in the substrate at sides of the spacer.

Abstract: A test element group for monitoring leakage current in a semiconductor device and a method of manufacturing the same are disclosed. The test element group for monitoring leakage current in a semiconductor device includes device isolation layers formed over a first conductivity type semiconductor substrate. A second conductivity type well may be formed over the first conductivity type semiconductor substrate. First conductivity type impurity regions may be formed in first active areas between the device isolation layers in the second conductivity type well. Monitoring contacts may be formed within the first active areas to monitor leakage current, using layout data such that a distance from each of the monitoring contacts to a border of each of the first active areas is set to have an allowable minimum value under a predetermined design rule.

Abstract: A test module for measuring electrical characteristics of a semiconductor device includes a plurality of shallow trench isolation (STI) layers formed over a semiconductor substrate. An active area includes not only an extended part enclosing the STI layers but also a plurality of minute line-width parts isolated by the STI layers. A gate oxide layer is formed over the STI layers and the active area. A gate electrode is formed over the STI layers and the minute line-width parts of the active area with interposing the gate oxide layer. An interlayer insulating layer, a metal wiring layer, a contact plug, and test pads allow non-destructive testing of the semiconductor device.

Abstract: A method of forming a metal line in a semiconductor device is disclosed. The method of forming a metal line in a semiconductor device includes forming an interlayer insulating film over a substrate. A via hole may be formed by selectively patterning the interlayer insulating film. A metal film may be formed over a surface of the interlayer insulating film including an inner portion of the via hole. The inner portion of the via hole may be filled with copper. A copper layer exposed over the surface of the interlayer insulating film may be deplated using reverse current to form a copper metal line and a recess region over the copper metal line. An upper insulating film may be formed over the surface of the interlayer insulating film including the recess region by deposition. An insulating cap layer may be selectively formed over only the recess region on the copper metal line by etching the upper insulating film.

Abstract: A semiconductor memory device includes a first active region formed having a first portion extending laterally and second portion extendedly vertically upward from a central portion of the first portion; a second active region formed spaced from the first active region, the second active region having a third portion extending laterally, fourth and fifth portions extending vertically downwardly at distal end portions of the third portion, and a sixth portion extending vertically downwardly at a central portion of the third portion; a first gate formed extending vertically and overlapping the first portion of the first active region and the third portion of the second active regions; a second gate formed extending vertically and overlapping the first portion of the first active region and the third portion of the second active regions; a third gate formed extending in a direction perpendicular to the first and second gates and overlapping of the fourth and fifth portions of the second active region; and a plur

Abstract: An image sensor including a second line formed at an upper part of a photodiode region as a transparent electrode for passing light. The second line is composed of a polymeric material having transparency and conductivity.

Abstract: An image sensor and a fabricating method thereof are provided. A pixel area and a peripheral circuit area can have a step difference on a semiconductor substrate. A Complimentary Metal Oxide Semiconductor (CMOS) circuit can be provided on the pixel area, and an interlayer dielectric layer can be provided on the pixel area and the peripheral circuit area. A photodiode can be provided on the interlayer dielectric layer of the pixel area such that the top of the photodiode, or an intrinsic layer of the photodiode, is about even with the top of the interlayer dielectric layer of the peripheral circuit area.

Abstract: A metal line of semiconductor device and a method of forming the same are provided. An interlayer dielectric (ILD) layer is formed on a semiconductor substrate including a lower line. A via hole is formed in the ILD layer, and a diffusion barrier layer is formed on the ILD layer where the via hole is formed. A copper seed layer and a copper plating layer are repeatedly formed and etched until the hole is completely filled.