Abstract: Heat exchanger comprising a pair of header tanks which are arranged to be spaced apart from each other, a plurality of tubes formed in two columns in the width direction so that both ends are connected to the pair of header tanks, and a plurality of fins interposed between the tubes and coupled to the tubes. The header tank is configured so that a first tank and a second tank are respectively coupled to one header having a central bent portion in the center portion in the width direction, which provides easy assembling of headers and tanks of two heat exchangers. Thermal stress caused by the temperature difference between two heat exchanging media is blocked so that damage to a coupling portion where the two heat exchangers are coupled or a bonding portion formed through brazing can be prevented. Thus, leakage of the heat exchanging medium can be prevented.

Abstract: Disclosure relates to an electrochemical lithium recovery system, and the electrochemical lithium recovery system is characterized by having a first flow electrode module that selectively extracts lithium ions from an object solution containing a waste battery active material by electrical attraction, and a second flow electrode module recovering the lithium ions extracted by the first flow electrode module, by the electric repulsive force. Accordingly, the electrochemical lithium recovery system does not require a high temperature treatment process, does not require a large amount of chemicals, and can ensure high recovery efficiency.

Abstract: An image sensor includes a substrate, a photoelectric conversion region in the substrate with the substrate defining a substrate trench on the photoelectric conversion region, a floating diffusion region adjacent to a side surface of the substrate trench, in the substrate, a gate dielectric film that extends along the side surface and a lower surface of the substrate trench and a transfer gate electrode which includes a lower gate that fills a portion of the substrate trench on the gate dielectric film and has a first width, and an upper gate that has a second width smaller than the first width on the lower gate. The gate dielectric film includes a lower dielectric film interposed between the substrate and the lower gate and has a first thickness, and an upper dielectric film adjacent to the floating diffusion region and has a second thickness greater than the first thickness.

Abstract: A flow-electrode cartridge unit and a submerged flow-electrode capacitive deionization device using the same are proposed. The flow-electrode cartridge unit includes a pair of porous current collector plates arranged to face each other in a spaced apart state from each other in a first direction, a pair of ion separation membranes positioned on respective outer surfaces of the porous current collector plates in the first direction, a channel frame for wrapping around the pair of porous current collector plates and the pair of ion separation membranes to expose each of the ion separation membranes in the first direction, thereby forming a flow electrode channel between the pair of porous current collector plates, a pair of communication holes formed in the channel frame and communicating the flow electrode channel to an outside, and an electrode terminal formed in the channel frame and electrically connected to the porous current collector plates.

Abstract: The present invention relates to an apparatus and a method for diagnosing a battery, and comprises: a power conversion unit for discharging and charging a battery; and a control unit for controlling the power conversion unit to discharge and charge the battery, and diagnosing power fade of the battery by calculating a maximum discharge output and a maximum charge output of the battery on the basis of a voltage and a current of the battery measured during discharging and charging of the battery.

Abstract: A transistor may include a semiconductor, a source electrode, a drain electrode, and a gate electrode. The semiconductor may include a first doped region, a second doped region, a source region, a drain region, and a channel region. The channel region is positioned between the source region and the drain region. The first doped region is positioned between the channel region and the source region. The second doped region is positioned between the channel region and the drain region. A doping concentration of the first doped region is lower than a doping concentration of the source region. A doping concentration of the second doped region is lower than a doping concentration of the drain region. The source electrode is electrically connected to the source region. The drain electrode is electrically connected to the drain region. The gate electrode overlaps the channel region.

Abstract: The present invention relates to an apparatus and a method for diagnosing a battery, and comprises: a power conversion unit for discharging and charging a battery; and a control unit for controlling the power conversion unit to discharge and charge the battery, and diagnosing power fade of the battery by calculating a maximum discharge output and a maximum charge output of the battery on the basis of a voltage and a current of the battery measured during discharging and charging of the battery.

Abstract: A transistor may include a semiconductor, a source electrode, a drain electrode, and a gate electrode. The semiconductor may include a first doped region, a second doped region, a source region, a drain region, and a channel region. The channel region is positioned between the source region and the drain region. The first doped region is positioned between the channel region and the source region. The second doped region is positioned between the channel region and the drain region. A doping concentration of the first doped region is lower than a doping concentration of the source region. A doping concentration of the second doped region is lower than a doping concentration of the drain region. The source electrode is electrically connected to the source region. The drain electrode is electrically connected to the drain region. The gate electrode overlaps the channel region.

Abstract: A transistor may include a semiconductor, a source electrode, a drain electrode, and a gate electrode. The semiconductor may include a first doped region, a second doped region, a source region, a drain region, and a channel region. The channel region is positioned between the source region and the drain region. The first doped region is positioned between the channel region and the source region. The second doped region is positioned between the channel region and the drain region. A doping concentration of the first doped region is lower than a doping concentration of the source region. A doping concentration of the second doped region is lower than a doping concentration of the drain region. The source electrode is electrically connected to the source region. The drain electrode is electrically connected to the drain region. The gate electrode overlaps the channel region.

Abstract: A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a substrate; a gate electrode on the substrate; a gate insulating layer on the gate electrode; a semiconductor member including a channel region overlapping the gate electrode with the gate insulating layer interposed therebetween, and a source region and a drain region that face each other with the channel region interposed therebetween; an interlayer insulating layer on the semiconductor member; a data conductor on the interlayer insulating layer; and a passivation layer on the data conductor, wherein the interlayer insulating layer has a first hole on the channel region.

Abstract: A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a substrate; a gate electrode on the substrate; a gate insulating layer on the gate electrode; a semiconductor member including a channel region overlapping the gate electrode with the gate insulating layer interposed therebetween, and a source region and a drain region that face each other with the channel region interposed therebetween; an interlayer insulating layer on the semiconductor member; a data conductor on the interlayer insulating layer; and a passivation layer on the data conductor, wherein the interlayer insulating layer has a first hole on the channel region.

Abstract: A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a substrate; a gate electrode on the substrate; a gate insulating layer on the gate electrode; a semiconductor member including a channel region overlapping the gate electrode with the gate insulating layer interposed therebetween, and a source region and a drain region that face each other with the channel region interposed therebetween; an interlayer insulating layer on the semiconductor member; a data conductor on the interlayer insulating layer; and a passivation layer on the data conductor, wherein the interlayer insulating layer has a first hole on the channel region.

Abstract: A thin film transistor array panel includes: a substrate; a semiconductor layer disposed on the substrate; a gate electrode disposed on the semiconductor layer; and a source electrode and a drain electrode disposed on the semiconductor layer to not overlap the gate electrode, wherein a first edge of the gate electrode is aligned with a second edge of the semiconductor layer in a direction that is perpendicular to the substrate.

Abstract: A transistor may include a semiconductor, a source electrode, a drain electrode, and a gate electrode. The semiconductor may include a first doped region, a second doped region, a source region, a drain region, and a channel region. The channel region is positioned between the source region and the drain region. The first doped region is positioned between the channel region and the source region. The second doped region is positioned between the channel region and the drain region. A doping concentration of the first doped region is lower than a doping concentration of the source region. A doping concentration of the second doped region is lower than a doping concentration of the drain region. The source electrode is electrically connected to the source region. The drain electrode is electrically connected to the drain region. The gate electrode overlaps the channel region.

Abstract: A display device includes: a plurality of pixels, wherein each of the plurality of pixels includes at least two double-gate transistors including a first gate electrode and a second gate electrode; conduction between source electrodes and drain electrodes of the at least two double-gate transistors is controlled by a voltage applied to the first gate electrode, and electrical connection between the second gate electrode and the first gate electrode of each of the at least two double-gate transistors is determined depending on a polarity of a voltage applied on average to each of the at least two double-gate transistors.

Abstract: A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a substrate; a gate electrode on the substrate; a gate insulating layer on the gate electrode; a semiconductor member including a channel region overlapping the gate electrode with the gate insulating layer interposed therebetween, and a source region and a drain region that face each other with the channel region interposed therebetween; an interlayer insulating layer on the semiconductor member; a data conductor on the interlayer insulating layer; and a passivation layer on the data conductor, wherein the interlayer insulating layer has a first hole on the channel region.

Abstract: A thin film transistor array panel includes: a substrate; a semiconductor layer disposed on the substrate; a gate electrode disposed on the semiconductor layer; and a source electrode and a drain electrode disposed on the semiconductor layer to not overlap the gate electrode, wherein a first edge of the gate electrode is aligned with a second edge of the semiconductor layer in a direction that is perpendicular to the substrate.

Abstract: A pixel circuit and a display device having the pixel circuit are disclosed. One inventive aspect includes a switching thin-film TFT and a light sensing TFT. The switching thin-film TFT includes a first source electrode electrically connected to a data line. A first gate electrode of the switching thin-film TFT and a second source electrode of the light sensing TFT are electrically connected to a first gate line. A first drain electrode of the switching thin-film TFT and a second drain electrode of the light sensing TFT are electrically connected to a pixel electrode.

Abstract: A thin film transistor substrate includes a substrate, a data line disposed on the substrate and which extends substantially in a predetermined direction, a light blocking layer disposed on the substrate and including a metal oxide including zinc manganese oxide, zinc cadmium oxide, zinc phosphorus oxide or zinc tin oxide, a gate electrode disposed on the light blocking layer, a signal electrode including a source electrode and a drain electrode spaced apart from the source electrode, where the source electrode is connected to the data line, and a semiconductor pattern disposed between the source electrode and the drain electrode.

Abstract: The inventive concept relates to a thin film transistor and a thin film transistor array panel and, in detail, relates to a thin film transistor including an oxide semiconductor. A thin film transistor according to an exemplary embodiment of the inventive concept includes: a gate electrode; a gate insulating layer positioned on or under the gate electrode; a first semiconductor and a second semiconductor that overlap the gate electrode with the gate insulating layer interposed therebetween, the first semiconductor and the second semiconductor contacting each other; a source electrode connected to the second semiconductor; and a drain electrode connected to the second semiconductor and facing the source electrode, wherein the second semiconductor includes gallium (Ga) that is not included in the first semiconductor, and a content of gallium (Ga) in the second semiconductor is greater than 0 at. % and less than or equal to about 33 at. %.