Patents by Inventor Ji-Hwan Hwang
Ji-Hwan Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145437Abstract: A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.Type: ApplicationFiled: January 10, 2024Publication date: May 2, 2024Inventors: JI-HWAN HWANG, SANG-SICK PARK, TAE-HONG MIN, GEOL NAM
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Patent number: 11953626Abstract: The present invention relates to a light detecting and ranging (LiDAR) device for obtaining information on a distance from an object using laser light.Type: GrantFiled: January 4, 2019Date of Patent: April 9, 2024Assignee: SOS Lab Co., LtdInventors: Ji Seong Jeong, Jun Hwan Jang, Dong Kyu Kim, Sung Hi Hwang
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Patent number: 11953596Abstract: A light detection and ranging (lidar) device includes: a lower base; an upper base; a laser emitting unit for emitting a laser in a form of a point light source; a nodding mirror for transforming the laser in the form of the point light source to a line beam pattern which is perpendicular to the lower base, wherein the nodding mirror reflects the laser emitted from the laser emitting unit; a polygonal mirror for transforming the line beam pattern to a plane beam pattern and receiving a laser reflected from an object; and a sensor unit for receiving the laser reflected from the object via the polygonal mirror.Type: GrantFiled: September 21, 2022Date of Patent: April 9, 2024Assignee: SOS Lab Co., Ltd.Inventors: Ji Seong Jeong, Jun Hwan Jang, Dong Kyu Kim, Sung Ui Hwang, Gyeong Hwan Shin, Bum Sik Won
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Patent number: 11945744Abstract: Disclosed are a method and apparatus for reusing wastewater. The method for reusing wastewater disclosed herein includes: generating a mixed wastewater by mixing multiple types of wastewater (S20); performing a first purification by passing the mixed wastewater through a flocculation-sedimentation unit (S40); performing a second purification by passing an effluent of the flocculation-sedimentation unit through a membrane bioreactor (MBR) (S60); performing a third purification by passing an effluent of the MBR through a reverse-osmosis membrane unit (S80); and reusing an effluent of the reverse-osmosis membrane unit as cooling water or industrial water (S100).Type: GrantFiled: April 14, 2023Date of Patent: April 2, 2024Assignees: SAMSUNG ENGINEERING CO., LTD., SAMSUNG ELECTRONICS CO., LTDInventors: Seok Hwan Hong, Dae Soo Park, Seung Joon Chung, Yong Xun Jin, Jae Hyung Park, Jae Hoon Choi, Jae Dong Hwang, Jong Keun Yi, Su Hyoung Cho, Kyu Won Hwang, June Yurl Hur, Je Hun Kim, Ji Won Chun
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Patent number: 11926558Abstract: The present specification relates to a conductive structure body, a method for manufacturing the same, and an electrode and an electronic device including the conductive structure body.Type: GrantFiled: March 28, 2016Date of Patent: March 12, 2024Assignee: LG CHEM LTD.Inventors: Ilha Lee, Seung Heon Lee, Song Ho Jang, Dong Hyun Oh, Ji Young Hwang, Ki-Hwan Kim, Han Min Seo, Chan Hyoung Park, Sun Young Park
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Patent number: 11912916Abstract: The present disclosure relates to an organic electroluminescent compound represented by formula 1 and an organic electroluminescent device comprising the same. By comprising the organic electroluminescent compound of the present disclosure, it is possible to provide an organic electroluminescent device having lower operating voltage, higher luminous efficiency and/or longer lifespan properties as compared with a conventional organic electroluminescent device.Type: GrantFiled: July 1, 2019Date of Patent: February 27, 2024Assignee: Rohm and Haas Electronic Materials Korea Ltd.Inventors: Hyun Kim, Ji-Song Jun, Jeong-Hwan Jeon, Yeon-Gun Lee, Seon-Jin Hwang, Young-Jun Cho
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Patent number: 11894346Abstract: A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.Type: GrantFiled: March 10, 2023Date of Patent: February 6, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-Hwan Hwang, Sang-Sick Park, Tae-Hong Min, Geol Nam
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Patent number: 11887900Abstract: A semiconductor package includes a base including a first bonding structure; and a first semiconductor chip, including a second bonding structure, the second bonding structure being coupled to the first bonding structure of the base, wherein the first bonding structure includes: a test pad; a first pad being electrically connected to the test pad; and a first insulating layer, wherein the second bonding structure includes: a second pad being electrically connected to the first pad; and a second insulating layer being in contact with the first insulating layer, and wherein at least a portion of the test pad is in contact with the second insulating layer.Type: GrantFiled: July 6, 2021Date of Patent: January 30, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyuek Jae Lee, Tae Hun Kim, Ji Hwan Hwang, Ji Hoon Kim, Ji Seok Hong
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Patent number: 11887968Abstract: A semiconductor package includes a base structure having a base pad, a first semiconductor chip on the base structure, and having a first connection pad bonded to the base pad, a first bonding structure including an base insulation layer of a base structure and a first lower insulation layer of the first semiconductor chip bonded to the base insulation layer, a second semiconductor chip on the first semiconductor chip, and having a second connection pad connected to the first through-electrode, and a second bonding structure including a first upper insulation layer of the first semiconductor chip, and a second lower insulation layer of the second semiconductor chip bonded to the first upper insulation layer, and the first upper insulation layer has a dummy insulation portion extending onto the base structure around the first semiconductor chip.Type: GrantFiled: October 5, 2021Date of Patent: January 30, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji Hwan Hwang, Ji Hoon Kim, Ji Seok Hong, Tae Hun Kim, Hyuek Jae Lee
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Publication number: 20230207533Abstract: A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.Type: ApplicationFiled: March 10, 2023Publication date: June 29, 2023Inventors: JI-HWAN HWANG, SANG-SICK PARK, TAE-HONG MIN, GEOL NAM
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Patent number: 11664352Abstract: A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.Type: GrantFiled: May 24, 2021Date of Patent: May 30, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Hwan Hwang, Sang-Sick Park, Tae-Hong Min, Geol Nam
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Patent number: 11581257Abstract: A semiconductor package is provided. The semiconductor package includes a lower structure including an upper insulating layer and an upper pad; and a semiconductor chip provided on the lower structure and comprising a lower insulating layer and a lower pad. The lower insulating layer is in contact with and coupled to the upper insulating layer and the lower pad is in contact with and coupled to the upper pad, and a lateral side of the semiconductor chip extends between an upper side and a lower side of the semiconductor chip and comprises a recessed portion.Type: GrantFiled: June 4, 2021Date of Patent: February 14, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyuek Jae Lee, Ji Hoon Kim, Tae Hun Kim, Ji Seok Hong, Ji Hwan Hwang
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Patent number: 11545458Abstract: A semiconductor package includes a first semiconductor chip including a first body portion, a first bonding layer including a first bonding insulating layer, a first redistribution portion including first redistribution layers, a first wiring insulating layer disposed between the first redistribution layers, and a second bonding layer including a second bonding insulating layer, a second redistribution portion including second redistribution layers, a second wiring insulating layer disposed between the second redistribution layers, and a second semiconductor chip disposed on the second redistribution portion. A lower surface of the first bonding insulating layer is bonded to an upper surface of the second bonding insulating layer, an upper surface of the first bonding insulating layer contacts the first body portion, a lower surface of the second bonding insulating layer contacts the second wiring insulating layer, and the first redistribution portion width is greater than the first semiconductor chip width.Type: GrantFiled: April 2, 2021Date of Patent: January 3, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun Chul Kim, Tae Hun Kim, Ji Hwan Hwang
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Publication number: 20220028837Abstract: A semiconductor package includes a base structure having a base pad, a first semiconductor chip on the base structure, and having a first connection pad bonded to the base pad, a first bonding structure including an base insulation layer of a base structure and a first lower insulation layer of the first semiconductor chip bonded to the base insulation layer, a second semiconductor chip on the first semiconductor chip, and having a second connection pad connected to the first through-electrode, and a second bonding structure including a first upper insulation layer of the first semiconductor chip, and a second lower insulation layer of the second semiconductor chip bonded to the first upper insulation layer, and the first upper insulation layer has a dummy insulation portion extending onto the base structure around the first semiconductor chip.Type: ApplicationFiled: October 5, 2021Publication date: January 27, 2022Inventors: Ji Hwan HWANG, Ji Hoon KIM, Ji Seok HONG, Tae Hun KIM, Hyuek Jae LEE
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Publication number: 20210335680Abstract: A semiconductor package includes a base including a first bonding structure; and a first semiconductor chip, including a second bonding structure, the second bonding structure being coupled to the first bonding structure of the base, wherein the first bonding structure includes: a test pad; a first pad being electrically connected to the test pad; and a first insulating layer, wherein the second bonding structure includes: a second pad being electrically connected to the first pad; and a second insulating layer being in contact with the first insulating layer, and wherein at least a portion of the test pad is in contact with the second insulating layer.Type: ApplicationFiled: July 6, 2021Publication date: October 28, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyuek Jae LEE, Tae Hun Kim, Ji Hwan Hwang, Ji Hoon Kim, Ji Seok Hong
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Patent number: 11145626Abstract: A semiconductor package includes a base structure having a base pad, a first semiconductor chip on the base structure, and having a first connection pad bonded to the base pad, a first bonding structure including an base insulation layer of a base structure and a first lower insulation layer of the first semiconductor chip bonded to the base insulation layer, a second semiconductor chip on the first semiconductor chip, and having a second connection pad connected to the first through-electrode, and a second bonding structure including a first upper insulation layer of the first semiconductor chip, and a second lower insulation layer of the second semiconductor chip bonded to the first upper insulation layer, and the first upper insulation layer has a dummy insulation portion extending onto the base structure around the first semiconductor chip.Type: GrantFiled: October 1, 2019Date of Patent: October 12, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Ji Hwan Hwang, Ji Hoon Kim, Ji Seok Hong, Tae Hun Kim, Hyuek Jae Lee
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Publication number: 20210296228Abstract: A semiconductor package is provided. The semiconductor package includes a lower structure including an upper insulating layer and an upper pad; and a semiconductor chip provided on the lower structure and comprising a lower insulating layer and a lower pad. The lower insulating layer is in contact with and coupled to the upper insulating layer and the lower pad is in contact with and coupled to the upper pad, and a lateral side of the semiconductor chip extends between an upper side and a lower side of the semiconductor chip and comprises a recessed portion.Type: ApplicationFiled: June 4, 2021Publication date: September 23, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyuek Jae Lee, Ji Hoon Kim, Tae Hun Kim, Ji Seok Hong, Ji Hwan Hwang
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Publication number: 20210280564Abstract: A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.Type: ApplicationFiled: May 24, 2021Publication date: September 9, 2021Inventors: JI-HWAN HWANG, SANG-SICK PARK, TAE-HONG MIN, GEOL NAM
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Patent number: 11088038Abstract: A semiconductor package includes a base including a first bonding structure; and a first semiconductor chip, including a second bonding structure, the second bonding structure being coupled to the first bonding structure of the base, wherein the first bonding structure includes: a test pad; a first pad being electrically connected to the test pad; and a first insulating layer, wherein the second bonding structure includes: a second pad being electrically connected to the first pad; and a second insulating layer being in contact with the first insulating layer, and wherein at least a portion of the test pad is in contact with the second insulating layer.Type: GrantFiled: July 11, 2019Date of Patent: August 10, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyuek Jae Lee, Tae Hun Kim, Ji Hwan Hwang, Ji Hoon Kim, Ji Seok Hong
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Publication number: 20210225796Abstract: A semiconductor package includes a first semiconductor chip including a first body portion, a first bonding layer including a first bonding insulating layer, a first redistribution portion including first redistribution layers, a first wiring insulating layer disposed between the first redistribution layers, and a second bonding layer including a second bonding insulating layer, a second redistribution portion including second redistribution layers, a second wiring insulating layer disposed between the second redistribution layers, and a second semiconductor chip disposed on the second redistribution portion. A lower surface of the first bonding insulating layer is bonded to an upper surface of the second bonding insulating layer, an upper surface of the first bonding insulating layer contacts the first body portion, a lower surface of the second bonding insulating layer contacts the second wiring insulating layer, and the first redistribution portion width is greater than the first semiconductor chip width.Type: ApplicationFiled: April 2, 2021Publication date: July 22, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun Chul KIM, Tae Hun KIM, Ji Hwan HWANG