Abstract: A method and apparatus for interfacing buses includes a system interface processor coupled to a first bus and including a command register accessible via a second bus. A request buffer and a response buffer are provided which are accessible via the second bus and coupled to the interface processor. The request buffer can be used to store information to be transmitted from the second bus to the first via the interface processor while the response buffer can be used to store information to be transmitted from the first bus to the second bus via the interface processor. The interface processor may include a status register to indicate the status of the interface controller. The interface controller may also include a command register to receive commands transmitted over the second bus.

Abstract: A method of recording events occurring in an information processing system in a memory unit. A system recorder is used as part of a server system which supports communication of digital information for a microcontroller network. The server system monitors the status of several system functions including temperature, cooling fan speeds, and the presence or absence of canisters and power supplies. The system updates the pertinent event messages and identification codes in the memory unit including the time such event or change in status occurred.

Abstract: A system recorder for logging events occurring in an information processing system in a memory unit. The system recorder is part of a server system which supports communication of digital information for a microcontroller network. The server system monitors the status of several system functions including temperature, cooling fan speeds, and the presence or absence of canisters and power supplies. The system updates the pertinent event messages and identification codes in the memory unit including the time such event or change in status occurred.

Abstract: A method of reporting a system failure in a server system, which includes the following acts: detecting a system failure condition; transmitting failure information related to the failure condition to a system recorder; storing the failure information into a system log; sending an event signal to a system interface; and reporting an occurrence of an event to a central processing unit of the server system.

Abstract: A method and apparatus for interfacing buses includes a system interface processor coupled to a first bus and including a command register accessible via a second bus. A request buffer and a response buffer are provided which are accessible via the second bus and coupled to the interface processor. The request buffer can be used to store information to be transmitted from the second bus to the first via the interface processor while the response buffer can be used to store information to be transmitted from the first bus to the second bus via the interface processor. The interface processor may include a status register to indicate the status of the interface controller. The interface controller may also include a command register to receive commands transmitted over the second bus.

Abstract: A system for reporting a failure condition in a server system which includes: a controller which monitors the server system for system failures, and generates an event signal and failure information if a system failure is detected; a system interface, coupled to the controller, which receives the event signal; a central processing unit, coupled to the system interface, wherein, upon receiving the event signal, the system interface reports an occurrence of an event to the central processing unit; and a system log which stores the failure information.

Abstract: A BIOS testing routine is initiated. Control is transferred to a diagnostic routine. The diagnostic routine performs a series of test in which a plurality of components are examined. In one embodiment, a random access/random data memory test is performed on a block of memory. Subsequently, control is transferred to the BIOS testing routine.

Abstract: A BIOS testing routine is initiated. Control is transferred to a diagnostic routine. The diagnostic routine performs a series of test in which a plurality of components are examined. In one embodiment, a random access/random data memory test is performed on a block of memory. Subsequently, control is transferred to the BIOS testing routine.

Abstract: A method and apparatus for interfacing buses includes a system interface processor coupled to a first bus and including a command register accessible via a second bus. A request buffer and a response buffer are provided which are accessible via the second bus and coupled to the interface processor. The request buffer can be used to store information to be transmitted from the second bus to the first via the interface processor while the response buffer can be used to store information to be transmitted from the first bus to the second bus via the interface processor. The interface processor may include a status register to indicate the status of the interface controller. The interface controller may also include a command register to receive commands transmitted over the second bus.