Abstract: A device for fixing a camera module, includes a base part; and a fixing unit including a first fixing part for supporting one side of each of a plurality of boards, and a second fixing part for supporting the other side facing one side of each of the plurality of boards, wherein a plurality of first fixing parts extends in a first direction from the base part, and includes a plurality of protruding parts protruding in the direction perpendicular to the first direction in order to support one side of each of the plurality of boards, and a plurality of second fixing parts extends in the first direction from the base part, and includes a plurality of protruding parts for supporting the other side of each of the plurality of boards.

Abstract: A semiconductor device includes a plurality of blocks on a substrate. Trenches are disposed between the plurality of blocks. Conductive patterns are formed inside the trenches. A lower end of an outermost trench among the trenches is formed at a level higher than a level of a lower end of the trench adjacent to the outermost trench. Each of the blocks includes insulating layers and gate electrodes, which are alternately and repeatedly stacked. Pillars pass through the insulating layers and the gate electrodes along a direction orthogonal to an upper surface of the substrate.

Abstract: A semiconductor device includes a plurality of blocks on a substrate. Trenches are disposed between the plurality of blocks. Conductive patterns are formed inside the trenches. A lower end of an outermost trench among the trenches is firmed at a level higher than a level of a lower end of the trench adjacent to the outermost trench. Each of the blocks includes insulating layers and gate electrodes, which are alternately and repeatedly stacked. Pillars pass through the insulating layers and the gate electrodes along a direction orthogonal to an upper surface of the substrate.

Abstract: A semiconductor device includes a plurality of blocks on a substrate. Trenches are disposed between the plurality of blocks. Conductive patterns are formed inside the trenches. A lower end of an outermost trench among the trenches is formed at a level higher than a level of a lower end of the trench adjacent to the outermost trench. Each of the blocks includes insulating layers and gate electrodes, which are alternately and repeatedly stacked. Pillars pass through the insulating layers and the gate electrodes along a direction orthogonal to an upper surface of the substrate.

Abstract: A semiconductor device includes a plurality of blocks on a substrate. Trenches are disposed between the plurality of blocks. Conductive patterns are formed inside the trenches. A lower end of an outermost trench among the trenches is formed at a level higher than a level of a lower end of the trench adjacent to the outermost trench. Each of the blocks includes insulating layers and gate electrodes, which are alternately and repeatedly stacked. Pillars pass through the insulating layers and the gate electrodes along a direction orthogonal to an upper surface of the substrate.

Abstract: A semiconductor device includes a plurality of blocks on a substrate. Trenches are disposed between the plurality of blocks. Conductive patterns are formed inside the trenches. A lower end of an outermost trench among the trenches is formed at a level higher than a level of a lower end of the trench adjacent to the outermost trench. Each of the blocks includes insulating layers and gate electrodes, which are alternately and repeatedly stacked. Pillars pass through the insulating layers and the gate electrodes along a direction orthogonal to an upper surface of the substrate.

Abstract: A vertical memory device includes a substrate having a cell array region and a connection region adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, and forming a stepped structure in the connection region, a first metal line dividing the plurality of gate electrode layers and connected to the cell array region and the connection region of the substrate, and a second metal line dividing a portion of the plurality of gate electrode layers and connected to the connection region of the substrate. A depth of a lower end portion of the second metal line may be greater than a depth of a lower end portion of the first metal line in the cell array region, based on an upper surface of the substrate.

Abstract: A method of controlling energy supply in a fuel cell vehicle includes storing an output current of a fuel cell as a pre-limited current when a cell voltage ratio reaches a minimum cell voltage ratio, setting a limited output current of the fuel cell as the pre-limited current when the cell voltage ratio reaches a hazard cell voltage ratio, connecting first and second high-voltage batteries to a main bus terminal in parallel when the cell voltage ratio reaches the hazard cell voltage ratio, and outputting a supplementary current from the second high-voltage battery by an insufficient amount of the output current of the fuel cell for the pre-limited current, and a system for performing the same.

Abstract: A vertical memory device includes a substrate having a cell array region and a connection region adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, and forming a stepped structure in the connection region, a first metal line dividing the plurality of gate electrode layers and connected to the cell array region and the connection region of the substrate, and a second metal line dividing a portion of the plurality of gate electrode layers and connected to the connection region of the substrate. A depth of a lower end portion of the second metal line may be greater than a depth of a lower end portion of the first metal line in the cell array region, based on an upper surface of the substrate.

Abstract: A vertical memory device includes a substrate having a cell array region and a connection region adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, and forming a stepped structure in the connection region, a first metal line dividing the plurality of gate electrode layers and connected to the cell array region and the connection region of the substrate, and a second metal line dividing a portion of the plurality of gate electrode layers and connected to the connection region of the substrate. A depth of a lower end portion of the second metal line may be greater than a depth of a lower end portion of the first metal line in the cell array region, based on an upper surface of the substrate.

Abstract: A semiconductor device includes a plurality of blocks on a substrate. Trenches are disposed between the plurality of blocks. Conductive patterns are formed inside the trenches. A lower end of an outermost trench among the trenches is formed at a level higher than a level of a lower end of the trench adjacent to the outermost trench. Each of the blocks includes insulating layers and gate electrodes, which are alternately and repeatedly stacked. Pillars pass through the insulating layers and the gate electrodes along a direction orthogonal to an upper surface of the substrate.

Abstract: A vertical memory device includes a substrate having a cell array region and a connection region adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, and forming a stepped structure in the connection region, a first metal line dividing the plurality of gate electrode layers and connected to the cell array region and the connection region of the substrate, and a second metal line dividing a portion of the plurality of gate electrode layers and connected to the connection region of the substrate. A depth of a lower end portion of the second metal line may be greater than a depth of a lower end portion of the first metal line in the cell array region, based on an upper surface of the substrate.

Abstract: A method of controlling energy supply in a fuel cell vehicle includes storing an output current of a fuel cell as a pre-limited current when a cell voltage ratio reaches a minimum cell voltage ratio, setting a limited output current of the fuel cell as the pre-limited current when the cell voltage ratio reaches a hazard cell voltage ratio, connecting first and second high-voltage batteries to a main bus terminal in parallel when the cell voltage ratio reaches the hazard cell voltage ratio, and outputting a supplementary current from the second high-voltage battery by an insufficient amount of the output current of the fuel cell for the pre-limited current, and a system for performing the same.

Abstract: A semiconductor device and a method for fabricating the same selectively forms a nitride layer having high tensile stress in an NMOS transistor area, to thereby form a strained-silicon structure in an NMOS channel region, whereby electron mobility is improved and drain current is increased. The semiconductor device includes an isolation region that, electrically isolates an N-type MOS transistor area from a P-type MOS transistor area, and a nitrade layer formed on an entire upper surface of a substrate, wherein the nitrade layer has silicon ions (Si+) selectively implanted in the P-type MOS transistor area.

Abstract: A method for manufacturing a CMOS image sensor is provided. A metal line can be formed over a semiconductor substrate including a transistor structure. Dangling bonding on the surface of the semiconductor substrate can be removed after forming the metal line by injecting a preset amount of hydrogen (H) atoms on the surface of the semiconductor substrate. Then, a thermal treatment can be performed on the resulting structure.

Abstract: A manufacturing method of a semiconductor device is disclosed whereby an oxide layer and a nitride layer are successively formed on a semiconductor substrate. An opening is then formed in the oxide and nitride layers on a field region of the semiconductor substrate. A trench is formed by etching the field region of the semiconductor substrate. The oxide layer and the nitride layer are then removed. A silicon epitaxial layer is grown on the semiconductor substrate including the trench, and finally an oxide layer is deposited in the trench. The silicon epitaxial layer has an increased thickness at the sidewall relative to the bottom face, such that the trench having a finer width is formed.

Abstract: A manufacturing method of a semiconductor device is disclosed whereby an oxide layer and a nitride layer are successively formed on a semiconductor substrate. An opening is then formed in the oxide and nitride layers on a field region of the semiconductor substrate. A trench is formed by etching the field region of the semiconductor substrate. The oxide layer and the nitride layer are then removed. A silicon epitaxial layer is grown on the semiconductor substrate including the trench, and finally an oxide layer is deposited in the trench. The silicon epitaxial layer has an increased thickness at the sidewall relative to the bottom face, such that the trench having a finer width is formed.