Patents by Inventor Ji Hwan Yu

Ji Hwan Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240308396
    Abstract: A device for height adjustment and swivel of a seat for a vehicle has a structure in which a first motor for height adjustment of the seat, a first reduction gear device for increasing output torque of the first motor, and a lifting device configured to lift or lower the seat by being connected to the first reduction gear device are stacked in a vertical direction, and a second motor for driving of seat swivel, a second reduction gear device for increasing output torque of the second motor, a brake device configured to stop the seat are vertically stacked between a bottom of the seat and the first motor, in order to adjust the height of the seat, enable accurate swiveling, and carry out a monopost function of the seat.
    Type: Application
    Filed: August 16, 2023
    Publication date: September 19, 2024
    Inventors: Ji Hwan Kim, Byung Yong Choi, So Young Yoo, Sang Uk Yu, Sang Ho Kim, Dong Woo Kim, Young Joon Kim, Jae Ho Kim, Ho Jin Jung
  • Publication number: 20240270125
    Abstract: A power swivel apparatus of a seat for a vehicle includes a motor having an eccentric shaft, a reduction gear device connected to the eccentric shaft of the motor, a brake device configured such that braking of the brake device is released by eccentric rotational force of the reduction gear at a time of driving the motor and the brake device exhibits braking force configured to stop the seat at a time of stopping driving of the motor, and a swivel plate connected to the brake device and configured to transmit rotational force so as to swivel the seat.
    Type: Application
    Filed: June 21, 2023
    Publication date: August 15, 2024
    Inventors: Ji Hwan Kim, Byung Yong Choi, So Young Yoo, Sang Uk Yu, Sang Ho Kim, Dong Woo Kim, Jae Ho Kim, Young Joon Kim, Ho Jin Jung
  • Publication number: 20240254103
    Abstract: The present invention relates to a novel pyrimidine derivative, and a composition for preventing or treating neurodegenerative diseases and cancer, comprising same, the pyrimidine derivative having a LRRK2 protein inhibitory activity, and effectively passing through a blood-brain barrier (BBB) so as to be effectively used as a pharmaceutical composition for preventing or treating neurodegenerative diseases and cancer.
    Type: Application
    Filed: March 12, 2021
    Publication date: August 1, 2024
    Applicants: WHAN IN PHARMACEUTICAL CO., LTD., KOREA RESEARCH INSTITUTE OF CHEMICAL TECHNOLOGY
    Inventors: Ge Hyeong LEE, Jee Yeon SEO, Jeong Heon YU, In Hae YE, Ho Chul SHIN, Jee Hee SUH, Seong Hwan KIM, Jin Sook SONG, Seong Hyeon SIM, Chong Hak CHAE, Hee Yeon KANG, Ji Hun LEE, Keon Ha HWANG
  • Publication number: 20240244971
    Abstract: The present disclosure relates to an organic light emitting diode including a first electrode; a second electrode facing the first electrode; and a first emitting part including a first blue emitting layer, a second blue emitting layer, an electron transporting layer and positioned between the first and second electrode, wherein the first blue emitting layer includes a first host and a first dopant, and the second blue emitting layer includes a second host and a second dopant, wherein the first host is an anthracene derivative having a first deuteration ratio, and the second host is an anthracene derivative having a second deuteration ratio smaller than the first deuteration ratio, wherein the first dopant is a first compound represented by Formula 3, and wherein the first electron transporting layer includes an electron transporting material represented by Formula 9.
    Type: Application
    Filed: September 18, 2023
    Publication date: July 18, 2024
    Applicant: LG DISPLAY CO., LTD.
    Inventors: Sang-Beom KIM, Young-Jun YU, Seon-Keun YOO, Dae-Wi YOON, Su-Na CHOI, Seong-Su JEON, Ji-Yun KIM, Yong-Hwan KIM, Jin-Hwan PARK
  • Publication number: 20240244843
    Abstract: A semiconductor device includes a plurality of blocks on a substrate. Trenches are disposed between the plurality of blocks. Conductive patterns are formed inside the trenches. A lower end of an outermost trench among the trenches is formed at a level higher than a level of a lower end of the trench adjacent to the outermost trench. Each of the blocks includes insulating layers and gate electrodes, which are alternately and repeatedly stacked. Pillars pass through the insulating layers and the gate electrodes along a direction orthogonal to an upper surface of the substrate.
    Type: Application
    Filed: March 27, 2024
    Publication date: July 18, 2024
    Inventors: Seung Hyun CHO, Kwang Ho LEE, Ji Hwan YU, Jong Soo KIM
  • Publication number: 20240244970
    Abstract: The present invention relates to an organic light emitting diode including first and second electrodes facing each other; and a first emitting part including a first blue emitting layer, a second blue emitting layer, an electron transporting layer and positioned between the first and second electrode, wherein the first blue emitting layer includes a first host and a first dopant, and the second blue emitting layer includes a second host and a second dopant, wherein the first host is an anthracene derivative having a first deuteration ratio, and the second host is an anthracene derivative having a second deuteration ratio smaller than the first deuteration ratio, wherein the first dopant is a first compound represented by Formula 3, and wherein the first electron transporting layer includes at least one of a first electron transporting material represented by Formula 9 and a second electron transporting material represented by Formula 10.
    Type: Application
    Filed: September 18, 2023
    Publication date: July 18, 2024
    Applicant: LG DISPLAY CO., LTD.
    Inventors: Sang-Beom KIM, Young-Jun YU, Seon-Keun YOO, Dae-Wi YOON, Su-Na CHOI, Seong-Su JEON, Ji-Yun KIM, Yong-Hwan KIM, Jin-Hwan PARK
  • Publication number: 20230081495
    Abstract: A semiconductor device includes a plurality of blocks on a substrate. Trenches are disposed between the plurality of blocks. Conductive patterns are formed inside the trenches. A lower end of an outermost trench among the trenches is formed at a level higher than a level of a lower end of the trench adjacent to the outermost trench. Each of the blocks includes insulating layers and gate electrodes, which are alternately and repeatedly stacked. Pillars pass through the insulating layers and the gate electrodes along a direction orthogonal to an upper surface of the substrate.
    Type: Application
    Filed: November 9, 2022
    Publication date: March 16, 2023
    Inventors: Seung Hyun CHO, Kwang Ho Lee, Ji Hwan Yu, Jong Soo Kim
  • Publication number: 20210313352
    Abstract: A semiconductor device includes a plurality of blocks on a substrate. Trenches are disposed between the plurality of blocks. Conductive patterns are formed inside the trenches. A lower end of an outermost trench among the trenches is firmed at a level higher than a level of a lower end of the trench adjacent to the outermost trench. Each of the blocks includes insulating layers and gate electrodes, which are alternately and repeatedly stacked. Pillars pass through the insulating layers and the gate electrodes along a direction orthogonal to an upper surface of the substrate.
    Type: Application
    Filed: June 22, 2021
    Publication date: October 7, 2021
    Inventors: Seung Hyun CHO, Kwang Ho LEE, Ji Hwan YU, Jong Soo KIM
  • Patent number: 11056506
    Abstract: A semiconductor device includes a plurality of blocks on a substrate. Trenches are disposed between the plurality of blocks. Conductive patterns are formed inside the trenches. A lower end of an outermost trench among the trenches is formed at a level higher than a level of a lower end of the trench adjacent to the outermost trench. Each of the blocks includes insulating layers and gate electrodes, which are alternately and repeatedly stacked. Pillars pass through the insulating layers and the gate electrodes along a direction orthogonal to an upper surface of the substrate.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: July 6, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung Hyun Cho, Kwang Ho Lee, Ji Hwan Yu, Jong Soo Kim
  • Publication number: 20200303412
    Abstract: A semiconductor device includes a plurality of blocks on a substrate. Trenches are disposed between the plurality of blocks. Conductive patterns are formed inside the trenches. A lower end of an outermost trench among the trenches is formed at a level higher than a level of a lower end of the trench adjacent to the outermost trench. Each of the blocks includes insulating layers and gate electrodes, which are alternately and repeatedly stacked. Pillars pass through the insulating layers and the gate electrodes along a direction orthogonal to an upper surface of the substrate.
    Type: Application
    Filed: June 2, 2020
    Publication date: September 24, 2020
    Inventors: Seung Hyun CHO, Kwang Ho LEE, Ji Hwan YU, Jong Soo KIM
  • Patent number: 10707229
    Abstract: A semiconductor device includes a plurality of blocks on a substrate. Trenches are disposed between the plurality of blocks. Conductive patterns are formed inside the trenches. A lower end of an outermost trench among the trenches is formed at a level higher than a level of a lower end of the trench adjacent to the outermost trench. Each of the blocks includes insulating layers and gate electrodes, which are alternately and repeatedly stacked. Pillars pass through the insulating layers and the gate electrodes along a direction orthogonal to an upper surface of the substrate.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: July 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung Hyun Cho, Kwang Ho Lee, Ji Hwan Yu, Jong Soo Kim
  • Patent number: 10644028
    Abstract: A vertical memory device includes a substrate having a cell array region and a connection region adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, and forming a stepped structure in the connection region, a first metal line dividing the plurality of gate electrode layers and connected to the cell array region and the connection region of the substrate, and a second metal line dividing a portion of the plurality of gate electrode layers and connected to the connection region of the substrate. A depth of a lower end portion of the second metal line may be greater than a depth of a lower end portion of the first metal line in the cell array region, based on an upper surface of the substrate.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: May 5, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwang Ho Lee, Kwang Ho Kim, Seung Hyun Cho, Ji Hwan Yu
  • Patent number: 10367216
    Abstract: A method of controlling energy supply in a fuel cell vehicle includes storing an output current of a fuel cell as a pre-limited current when a cell voltage ratio reaches a minimum cell voltage ratio, setting a limited output current of the fuel cell as the pre-limited current when the cell voltage ratio reaches a hazard cell voltage ratio, connecting first and second high-voltage batteries to a main bus terminal in parallel when the cell voltage ratio reaches the hazard cell voltage ratio, and outputting a supplementary current from the second high-voltage battery by an insufficient amount of the output current of the fuel cell for the pre-limited current, and a system for performing the same.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: July 30, 2019
    Assignees: Hyundai Motor Company, Kia Motors Corporation
    Inventors: Young Pin Jin, Sung Ho Yang, Jae Young Shim, Kang Sik Jeon, Ji Hwan Yu
  • Publication number: 20190214407
    Abstract: A vertical memory device includes a substrate having a cell array region and a connection region adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, and forming a stepped structure in the connection region, a first metal line dividing the plurality of gate electrode layers and connected to the cell array region and the connection region of the substrate, and a second metal line dividing a portion of the plurality of gate electrode layers and connected to the connection region of the substrate. A depth of a lower end portion of the second metal line may be greater than a depth of a lower end portion of the first metal line in the cell array region, based on an upper surface of the substrate.
    Type: Application
    Filed: March 19, 2019
    Publication date: July 11, 2019
    Inventors: KWANG HO LEE, Kwang Ho Kim, Seung-Hyun Cho, Ji Hwan Yu
  • Patent number: 10276591
    Abstract: A vertical memory device includes a substrate having a cell array region and a connection region adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, and forming a stepped structure in the connection region, a first metal line dividing the plurality of gate electrode layers and connected to the cell array region and the connection region of the substrate, and a second metal line dividing a portion of the plurality of gate electrode layers and connected to the connection region of the substrate. A depth of a lower end portion of the second metal line may be greater than a depth of a lower end portion of the first metal line in the cell array region, based on an upper surface of the substrate.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: April 30, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwang Ho Lee, Kwang Ho Kim, Seung Hynu Cho, Ji Hwan Yu
  • Publication number: 20190067320
    Abstract: A semiconductor device includes a plurality of blocks on a substrate. Trenches are disposed between the plurality of blocks. Conductive patterns are formed inside the trenches. A lower end of an outermost trench among the trenches is formed at a level higher than a level of a lower end of the trench adjacent to the outermost trench. Each of the blocks includes insulating layers and gate electrodes, which are alternately and repeatedly stacked. Pillars pass through the insulating layers and the gate electrodes along a direction orthogonal to an upper surface of the substrate.
    Type: Application
    Filed: March 30, 2018
    Publication date: February 28, 2019
    Inventors: Seung Hyun Cho, Kwang Ho Lee, Ji Hwan Yu, Jong Soo Kim
  • Publication number: 20190027491
    Abstract: A vertical memory device includes a substrate having a cell array region and a connection region adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, and forming a stepped structure in the connection region, a first metal line dividing the plurality of gate electrode layers and connected to the cell array region and the connection region of the substrate, and a second metal line dividing a portion of the plurality of gate electrode layers and connected to the connection region of the substrate. A depth of a lower end portion of the second metal line may be greater than a depth of a lower end portion of the first metal line in the cell array region, based on an upper surface of the substrate.
    Type: Application
    Filed: March 28, 2018
    Publication date: January 24, 2019
    Inventors: KWANG HO LEE, Kwang Ho KIM, Seung Hynu CHO, Ji Hwan YU
  • Publication number: 20180198144
    Abstract: A method of controlling energy supply in a fuel cell vehicle includes storing an output current of a fuel cell as a pre-limited current when a cell voltage ratio reaches a minimum cell voltage ratio, setting a limited output current of the fuel cell as the pre-limited current when the cell voltage ratio reaches a hazard cell voltage ratio, connecting first and second high-voltage batteries to a main bus terminal in parallel when the cell voltage ratio reaches the hazard cell voltage ratio, and outputting a supplementary current from the second high-voltage battery by an insufficient amount of the output current of the fuel cell for the pre-limited current, and a system for performing the same.
    Type: Application
    Filed: June 14, 2017
    Publication date: July 12, 2018
    Inventors: Young Pin JIN, Sung Ho YANG, Jae Young SHIM, Kang Sik JEON, Ji Hwan YU
  • Patent number: 7588987
    Abstract: A semiconductor device and a method for fabricating the same selectively forms a nitride layer having high tensile stress in an NMOS transistor area, to thereby form a strained-silicon structure in an NMOS channel region, whereby electron mobility is improved and drain current is increased. The semiconductor device includes an isolation region that, electrically isolates an N-type MOS transistor area from a P-type MOS transistor area, and a nitrade layer formed on an entire upper surface of a substrate, wherein the nitrade layer has silicon ions (Si+) selectively implanted in the P-type MOS transistor area.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: September 15, 2009
    Assignee: Dongbu Electronics, Co., Ltd.
    Inventor: Ji Hwan Yu
  • Publication number: 20080153219
    Abstract: A method for manufacturing a CMOS image sensor is provided. A metal line can be formed over a semiconductor substrate including a transistor structure. Dangling bonding on the surface of the semiconductor substrate can be removed after forming the metal line by injecting a preset amount of hydrogen (H) atoms on the surface of the semiconductor substrate. Then, a thermal treatment can be performed on the resulting structure.
    Type: Application
    Filed: October 30, 2007
    Publication date: June 26, 2008
    Inventor: Ji Hwan Yu