Patents by Inventor Ji-Hyae Bae
Ji-Hyae Bae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11216596Abstract: A semiconductor system in accordance with an embodiment includes a module controller and a plurality of semiconductor chips configured to receive logical addresses from the module controller. The semiconductor system also includes a plurality of scramble circuits, with a scramble circuit provided for each of the plurality of semiconductor chips, configured to receive the logical addresses and to output corresponding physical addresses for the plurality of semiconductor chips. Each scramble circuit of the plurality of scramble circuits is configured to receive the same logical address and to output a corresponding physical address different from the physical addresses output by the other scramble circuits of the plurality of scramble circuits.Type: GrantFiled: November 18, 2019Date of Patent: January 4, 2022Assignee: SK hynix Inc.Inventor: Ji Hyae Bae
-
Publication number: 20200265171Abstract: A semiconductor system in accordance with an embodiment includes a module controller and a plurality of semiconductor chips configured to receive logical addresses from the module controller. The semiconductor system also includes a plurality of scramble circuits, with a scramble circuit provided for each of the plurality of semiconductor chips, configured to receive the logical addresses and to output corresponding physical addresses for the plurality of semiconductor chips. Each scramble circuit of the plurality of scramble circuits is configured to receive the same logical address and to output a corresponding physical address different from the physical addresses output by the other scramble circuits of the plurality of scramble circuits.Type: ApplicationFiled: November 18, 2019Publication date: August 20, 2020Applicant: SK hynix Inc.Inventor: Ji Hyae BAE
-
Patent number: 9997216Abstract: A nonvolatile random access memory including a memory cell array including banks, each bank including rows; an address latch circuit; and a control circuit receiving a first set of signals including a precharge command and a first row address, and a second set of signals including an active command and a second row address. The control circuit executes a first operation in which one of the banks is deactivated when the first set of signals is loaded, executes a second operation in which the first row address is loaded when the first set of signals is loaded, and executes a third operation in which at least one of the rows in the bank is selected and activated based on the second row address when the second set of signals is loaded after the first set of signals.Type: GrantFiled: February 24, 2017Date of Patent: June 12, 2018Assignees: TOSHIBA MEMORY CORPORATION, SK HYNIX INC.Inventors: Yutaka Shirai, Naoki Shimizu, Kenji Tsuchida, Yoji Watanabe, Ji Hyae Bae, Yong Ho Kim
-
Patent number: 9805781Abstract: A method of controlling a magnetoresistive random access memory includes receiving first signals associated with an active state through command/address pins; then receiving second signals associated with column and row addresses for a read operation, through the command/address pins, and in response reading data from a memory cell according to the row address; receiving third signals associated with column and row addresses for a write operation through the command/address pins, while reading the data; outputting the read data to data input/output pins, according to the column address for the read operation, after a lapse of a read latency; inputting data through the data input/output pins, in response to the third signals, according to the column address for the write operation, after a lapse of a write latency; and writing the data inputted from the data input/output pins to a memory cell according to the row address for the write operation.Type: GrantFiled: November 30, 2016Date of Patent: October 31, 2017Assignees: KABUSHIKI KAISHA TOSHIBA, SK HYNIX INC.Inventors: Naoki Shimizu, Ji Hyae Bae
-
Patent number: 9721635Abstract: Provided are, among others, memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic device which includes two variable resistance elements in each storage cell, thereby increasing margin and speed of a read operation. One disclosed electronic device includes a semiconductor memory unit which, in one implementation, in addition to two variable resistance elements, further includes a bit line and a bit line bar formed at a metal level; a first word line formed at a transistor level lower than the metal level, and extended in a direction perpendicular to the bit line or the bit line bar; a first selecting element formed at the transistor level and coupled to the bit line and the first word line; a second selecting element formed at the transistor level and coupled to the bit line bar and the first word line.Type: GrantFiled: September 30, 2014Date of Patent: August 1, 2017Assignee: SK hynix Inc.Inventors: Min-Hye Lee, Ji-Hyae Bae, Yong-Ho Kim
-
Patent number: 9691456Abstract: A reconfigurable semiconductor memory apparatus may include a memory cell array including a plurality of sub arrays. The reconfigurable semiconductor memory apparatus may include an information storage unit configured to store status information for each sub array, and a reset address according to the status information.Type: GrantFiled: April 13, 2015Date of Patent: June 27, 2017Assignee: SK hynix Inc.Inventors: Bo Ra Choi, Ji Hyae Bae, Jun Gi Choi
-
Publication number: 20170169869Abstract: A nonvolatile random access memory including a memory cell array including banks, each bank including rows; an address latch circuit; and a control circuit receiving a first set of signals including a precharge command and a first row address, and a second set of signals including an active command and a second row address. The control circuit executes a first operation in which one of the banks is deactivated when the first set of signals is loaded, executes a second operation in which the first row address is loaded when the first set of signals is loaded, and executes a third operation in which at least one of the rows in the bank is selected and activated based on the second row address when the second set of signals is loaded after the first set of signals.Type: ApplicationFiled: February 24, 2017Publication date: June 15, 2017Applicants: KABUSHIKI KAISHA TOSHIBA, SK HYNIX INC.Inventors: Yutaka SHIRAI, Naoki SHIMIZU, Kenji TSUCHIDA, Yoji WATANABE, Ji Hyae BAE, Yong Ho KIM
-
Patent number: 9613671Abstract: According to one embodiment, a memory includes a memory cell array with banks, each bank including rows, a first word lines provided in corresponding to the rows, an address latch circuit which latches a first row address signal, a row decoder which activates one of the first word lines, and a control circuit which is configured to execute a first operation which activates one of the banks based on a bank address signal when a first command is loaded, and a second operation which latches the first row address signal in the address latch circuit, and execute a third operation which activates one of the first word lines by the row decoder based on a second row address signal and the first row address signal latched in the address latch circuit when a second command is loaded after the first command.Type: GrantFiled: April 21, 2015Date of Patent: April 4, 2017Assignees: KABUSHIKI KAISHA TOSHIBA, SK HYNIX INC.Inventors: Yutaka Shirai, Naoki Shimizu, Kenji Tsuchida, Yoji Watanabe, Ji Hyae Bae, Yong Ho Kim
-
Publication number: 20170084325Abstract: A method of controlling a magnetoresistive random access memory includes receiving first signals associated with an active state through command/address pins; then receiving second signals associated with column and row addresses for a read operation, through the command/address pins, and in response reading data from a memory cell according to the row address; receiving third signals associated with column and row addresses for a write operation through the command/address pins, while reading the data; outputting the read data to data input/output pins, according to the column address for the read operation, after a lapse of a read latency; inputting data through the data input/output pins, in response to the third signals, according to the column address for the write operation, after a lapse of a write latency; and writing the data inputted from the data input/output pins to a memory cell according to the row address for the write operation.Type: ApplicationFiled: November 30, 2016Publication date: March 23, 2017Applicants: KABUSHIKI KAISHA TOSHIBA, SK hynix Inc.Inventors: Naoki SHIMIZU, Ji Hyae BAE
-
Patent number: 9583161Abstract: A memory apparatus includes a first memory bank, a second memory bank, a row decoder and repair circuit, and an input/output driver controller. The row decoder and repair circuit is coupled to the first and second memory banks in common. The row decoder and repair circuit generates a shared repair signal according to whether a word line disposed in a first memory bank is replaced with a word line disposed in a second memory bank. The input/output driver controller allows read or write operations for one of the first and second memory banks to be performed based on the shared repair signal and an operation signal.Type: GrantFiled: August 25, 2016Date of Patent: February 28, 2017Assignee: SK hynix Inc.Inventors: Yong Seop Kim, Ji Hyae Bae, Min Chul Shin, Jun Gi Choi
-
Patent number: 9530480Abstract: A semiconductor memory device is capable of executing a first mode having a first latency and a second mode having a second latency longer than the first latency. The semiconductor memory device includes: a pad unit configured to receive an address and a command from an outside; a first delay circuit configured to delay the address by a time corresponding to the first latency; a second delay circuit including shift registers connected in series and configured to delay the address by a time corresponding to a difference between the first latency and the second latency; and a controller configured to use the first delay circuit and the second delay circuit when executing the second mode.Type: GrantFiled: September 24, 2015Date of Patent: December 27, 2016Assignees: KABUSHIKI KAISHA TOSHIBA, SK HYNIX INCInventors: Naoki Shimizu, Ji Hyae Bae
-
Patent number: 9508457Abstract: An electronic device comprising a semiconductor memory unit that may include a plurality of data transfer lines; a plurality of columns including a plurality of memory cells; at least one redundancy column including a plurality of redundancy memory cells and configured to replace at least one column among the plurality of columns; a repair select information generation unit configured to store a column address of the at least one column to be replaced among the plurality of columns and generate a plurality of repair select information in response to the stored column address; and a plurality of repair selection units connected with data transfer lines corresponding to them among the plurality of data transfer lines, columns corresponding to them among the plurality of columns and the at least one redundancy column, and each configured to electrically connect a column selected among a column corresponding to it and the at least one redundancy column, to a data transfer line corresponding to it, in response toType: GrantFiled: January 15, 2016Date of Patent: November 29, 2016Assignee: SK hynix Inc.Inventors: Ji-Hyae Bae, Dong-Keun Kim
-
Patent number: 9489298Abstract: Provided is a nonvolatile memory apparatus which writes data into a memory cell according to a program and verify (PNV) operation, wherein the nonvolatile memory apparatus performs the PNV operation for first data during a first time, and performs a plurality of PNV operations for second data during the first time.Type: GrantFiled: March 18, 2013Date of Patent: November 8, 2016Assignee: SK HYNIX INC.Inventors: In Soo Lee, Ji Hyae Bae
-
Publication number: 20160217841Abstract: A reconfigurable semiconductor memory apparatus may include a memory cell array including a plurality of sub arrays. The reconfigurable semiconductor memory apparatus may include an information storage unit configured to store status information for each sub array, and a reset address according to the status information.Type: ApplicationFiled: April 13, 2015Publication date: July 28, 2016Inventors: Bo Ra CHOI, Ji Hyae BAE, Jun Gi CHOI
-
Publication number: 20160133343Abstract: An electronic device comprising a semiconductor memory unit that may include a plurality of data transfer lines; a plurality of columns including a plurality of memory cells; at least one redundancy column including a plurality of redundancy memory cells and configured to replace at least one column among the plurality of columns; a repair select information generation unit configured to store a column address of the at least one column to be replaced among the plurality of columns and generate a plurality of repair select information in response to the stored column address; and a plurality of repair selection units connected with data transfer lines corresponding to them among the plurality of data transfer lines, columns corresponding to them among the plurality of columns and the at least one redundancy column, and each configured to electrically connect a column selected among a column corresponding to it and the at least one redundancy column, to a data transfer line corresponding to it, in response toType: ApplicationFiled: January 15, 2016Publication date: May 12, 2016Inventors: Ji-Hyae Bae, Dong-Keun Kim
-
Patent number: 9240251Abstract: An electronic device comprising a semiconductor memory unit that may include a plurality of data transfer lines; a plurality of columns including a plurality of memory cells; at least one redundancy column including a plurality of redundancy memory cells and configured to replace at least one column among the plurality of columns; a repair select information generation unit configured to store a column address of the at least one column to be replaced among the plurality of columns and generate a plurality of repair select information in response to the stored column address; and a plurality of repair selection units connected with data transfer lines corresponding to them among the plurality of data transfer lines, columns corresponding to them among the plurality of columns and the at least one redundancy column, and each configured to electrically connect a column selected among a column corresponding to it and the at least one redundancy column, to a data transfer line corresponding to it, in response toType: GrantFiled: July 24, 2015Date of Patent: January 19, 2016Assignee: SK hynix Inc.Inventors: Ji-Hyae Bae, Dong-Keun Kim
-
Publication number: 20160012875Abstract: A semiconductor memory device is capable of executing a first mode having a first latency and a second mode having a second latency longer than the first latency. The semiconductor memory device includes: a pad unit configured to receive an address and a command from an outside; a first delay circuit configured to delay the address by a time corresponding to the first latency; a second delay circuit including shift registers connected in series and configured to delay the address by a time corresponding to a difference between the first latency and the second latency; and a controller configured to use the first delay circuit and the second delay circuit when executing the second mode.Type: ApplicationFiled: September 24, 2015Publication date: January 14, 2016Inventors: Naoki SHIMIZU, Ji Hyae BAE
-
Publication number: 20150332791Abstract: An electronic device comprising a semiconductor memory unit that may include a plurality of data transfer lines; a plurality of columns including a plurality of memory cells; at least one redundancy column including a plurality of redundancy memory cells and configured to replace at least one column among the plurality of columns; a repair select information generation unit configured to store a column address of the at least one column to be replaced among the plurality of columns and generate a plurality of repair select information in response to the stored column address; and a plurality of repair selection units connected with data transfer lines corresponding to them among the plurality of data transfer lines, columns corresponding to them among the plurality of columns and the at least one redundancy column, and each configured to electrically connect a column selected among a column corresponding to it and the at least one redundancy column, to a data transfer line corresponding to it, in response toType: ApplicationFiled: July 24, 2015Publication date: November 19, 2015Inventors: Ji-Hyae Bae, Dong-Keun Kim
-
Patent number: 9171600Abstract: A semiconductor memory device is capable of executing a first mode having a first latency and a second mode having a second latency longer than the first latency. The semiconductor memory device includes: a pad unit configured to receive an address and a command from an outside; a first delay circuit configured to delay the address by a time corresponding to the first latency; a second delay circuit including shift registers connected in series and configured to delay the address by a time corresponding to a difference between the first latency and the second latency; and a controller configured to use the first delay circuit and the second delay circuit when executing the second mode.Type: GrantFiled: March 7, 2014Date of Patent: October 27, 2015Inventors: Naoki Shimizu, Ji Hyae Bae
-
Publication number: 20150302925Abstract: Disclosed is an electronic device including a semiconductor memory. The semiconductor memory includes a bit line, a source line, a plurality of resistive memory cells among which a selected resistive memory cell forms a current path between the bit line and the source line, a sense amplifier suitable for sensing data of the bit line in an active operation, a latch suitable for latching data sensed by the sense amplifier in the active operation, a write control unit suitable for comparing data latched in the latch with write data in a write operation, and a write driver suitable for driving the bit line and the source line based on a comparison result of the write control unit and the write data in the write operation.Type: ApplicationFiled: December 4, 2014Publication date: October 22, 2015Inventors: Byoung-Chan OH, Ji-Hyae BAE, Katsuyuki FUJITA, Yutaka SHIRAI