Abstract: Memory bank redistribution based on power consumption of multiple memory banks of a memory die can provide an overall reduced power consumption of a memory device. The respective power consumption of each bank can be determined and memory operations to the banks can be distributed based on the determined power consumption. The memory die can include an interface coupled to each bank. Control circuitry can remap logical to physical addresses of the banks based on one or more parameters such as a power consumption of each bank, counts of memory operations for each bank, and/or a relative physical distance of each bank.

Abstract: An on-die logic analyzer (ODLA) can reduce the time and resources that would otherwise be spent in validating or debugging memory system timings. The ODLA can receive an enable signal with respect to a start command and start a count of clock cycles in response to a first issued command matching the start command defined in a first mode register. The ODLA can stop the count of clock cycles in response to a second issued command matching a stop command defined in a second mode register. The ODLA can write a value indicative of the stopped count to a third mode register or an on-die storage array in response to the stopped count exceeding a previously stored count.

Abstract: Memory bank remapping based on sensed temperatures of a memory device can provide an overall reduced power consumption of the memory device. Signaling indicative of sensed temperatures detected by a plurality of temperature sensors within a stack of memory dies of a memory device can be received by address circuitry of the memory device. Based on the sensed temperatures and respective positions of the temperature sensors within the stack of memory dies, a portion of the memory device experiencing an excessive operating temperature can be identified. Logical addresses of a first memory bank of a memory die of the stack of memory dies near or at least partially within the identified portion can be remapped to physical addresses of a second memory bank of the memory die that is further away from the identified portion than the first memory bank.

Abstract: Memory bank redistribution based on power consumption of multiple memory banks of a memory die can provide an overall reduced power consumption of a memory device. The respective power consumption of each bank can be determined and memory operations to the banks can be distributed based on the determined power consumption. The memory die can include an interface coupled to each bank. Control circuitry can remap logical to physical addresses of the banks based on one or more parameters such as a power consumption of each bank, counts of memory operations for each bank, and/or a relative physical distance of each bank.

Abstract: An on-die logic analyzer (ODLA) can reduce the time and resources that would otherwise be spent in validating or debugging memory system timings. The ODLA can receive an enable signal with respect to a start command and start a count of clock cycles in response to a first issued command matching the start command defined in a first mode register. The ODLA can stop the count of clock cycles in response to a second issued command matching a stop command defined in a second mode register. The ODLA can write a value indicative of the stopped count to a third mode register or an on-die storage array in response to the stopped count exceeding a previously stored count.

Abstract: An on-die logic analyzer (ODLA) can reduce the time and resources that would otherwise be spent in validating or debugging memory system timings. The ODLA can receive an enable signal with respect to a start command and start a count of clock cycles in response to a first issued command matching the start command defined in a first mode register. The ODLA can stop the count of clock cycles in response to a second issued command matching a stop command defined in a second mode register. The ODLA can write a value indicative of the stopped count to a third mode register or an on-die storage array in response to the stopped count exceeding a previously stored count.

Abstract: An on-die logic analyzer (ODLA) can reduce the time and resources that would otherwise be spent in validating or debugging memory system timings. The ODLA can receive an enable signal with respect to a start command and start a count of clock cycles in response to a first issued command matching the start command defined in a first mode register. The ODLA can stop the count of clock cycles in response to a second issued command matching a stop command defined in a second mode register. The ODLA can write a value indicative of the stopped count to a third mode register or an on-die storage array in response to the stopped count exceeding a previously stored count.