Abstract: The present invention discloses a semiconductor memory device having a multiple tunnel junction pattern and a method of forming the same. The semiconductor memory device includes a unit cell composed of planar transistor and vertical transistors. The planar transistor includes first and second conductive regions formed at predetermined regions of a semiconductor substrate and a storage node stacked on a channel region therebetween. The vertical transistor includes a storage node, a multiple tunnel junction pattern stacked thereon, a data line stacked thereon, and a word line for covering both sidewalls of the storage node and the multiple tunnel junction pattern. Width of the multiple tunnel junction pattern is narrower than the storage node and data lines. Semiconductor layers and tunnel oxide layers are alternately and repeatedly stacked and anisotropically etched to form the multiple tunnel junction pattern of narrow width while forming the data line and the storage node.

Abstract: In one embodiment, a phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation and a method of manufacturing the same. In one embodiment, a semiconductor memory device comprises a molding layer overlying a semiconductor substrate. The molding layer has a protrusion portion vertically extending from a top surface thereof. The device further includes a phase-changeable material pattern adjacent the protrusion portion and a lower electrode electrically connected to the phase-changeable material pattern.

Abstract: Phase change memory devices include a phase-change memory layer on a semiconductor substrate. The phase-change memory layer has a major axis that is substantially parallel to a major axis of the semiconductor substrate and has a first surface and a second surface opposite the first surface that are substantially parallel to the major axis of the phase-change memory layer. A first electrode is provided on the semiconductor substrate that is electrically connected to the first surface of the phase-change memory layer in a first contact region of the phase-change memory layer. A second electrode is provided on the semiconductor substrate that is electrically connected to the phase-change memory layer in a second contact region of the phase-change memory layer. The second contact region is space apart from the first contact region.

Abstract: A system and method for synchronizing Broadcast/Multicast Service (BCMCS) traffic in a mobile communication system connected to a BCMCS server. A Packet Data Service Node (PDSN) receives a BCMCS content frame from the BCMCS server, and transmits a corresponding Generic Routing Encapsulation (GRE) packet BCMCS content frame, including a sequence number and a timestamp value indicating when the GRE packet BCMCS content frame is transmitted, to Packet Control Functions (PCF) connected downstream of the PDSN. Each of the PCFs determines whether the GRE packet BCMCS content frame received from the PDSN is valid, based on the sequence number included therein. If the GRE packet BCMCS content frame is valid, the PCF transmits the frame to its lower nodes connected downstream of the PCF, while synchronizing the frame transmission, based on the timestamp value included in the frame.

Abstract: In the method of programming a phase change memory cell, having a lower resistive state and a higher resistive state, to the lower resistive state, the memory cell is heated to first temperature. Subsequently, the memory cell is heated to second temperature, which is greater than the first temperature.

Abstract: Phase-changeable memory devices and method of fabricating phase-changeable memory devices are provided that include a phase-changeable material pattern of a phase-changeable material that may include nitrogen atoms and/or silicon atoms. First and second electrodes are electrically connected to the phase-changeable material pattern and provide an electrical signal thereto. The phase-changeable material pattern may have a polycrystalline structure.

Abstract: A phase-changeable memory device may include a substrate, an insulating layer on the substrate, first and second electrodes, and a pattern of a phase-changeable material between the first and second electrodes. More particularly, the insulating layer may have a hole therein, and the first electrode may be in the hole in the insulating layer. Moreover, portions of the second electrode may extend beyond an edge of the pattern of phase-changeable material. Related methods are also discussed.

Abstract: Phase change memory devices include a phase-change memory layer on a semiconductor substrate. The phase-change memory layer has a major axis that is substantially parallel to a major axis of the semiconductor substrate and has a first surface and a second surface opposite the first surface that are substantially parallel to the major axis of the phase-change memory layer. A first electrode is provided on the semiconductor substrate that is electrically connected to the first surface of the phase-change memory layer in a first contact region of the phase-change memory layer. A second electrode is provided on the semiconductor substrate that is electrically connected to the phase-change memory layer in a second contact region of the phase-change memory layer. The second contact region is space apart from the first contact region.

Abstract: The present invention discloses a semiconductor memory device having a multiple tunnel junction pattern and a method of forming the same. The semiconductor memory device includes a unit cell composed of planar transistor and vertical transistors. The planar transistor includes first and second conductive regions formed at predetermined regions of a semiconductor substrate and a storage node stacked on a channel region therebetween. The vertical transistor includes a storage node, a multiple tunnel junction pattern stacked thereon, a data line stacked thereon, and a word line for covering both sidewalls of the storage node and the multiple tunnel junction pattern. Width of the multiple tunnel junction pattern is narrower than the storage node and data lines. Semiconductor layers and tunnel oxide layers are alternately and repeatedly stacked and anisotropically etched to form the multiple tunnel junction pattern of narrow width while forming the data line and the storage node.

Abstract: The present invention discloses a semiconductor memory device having a multiple tunnel junction pattern and a method of forming the same. The semiconductor memory device includes a unit cell composed of planar transistor and vertical transistors. The planar transistor includes first and second conductive regions formed at predetermined regions of a semiconductor substrate and a storage node stacked on a channel region therebetween. The vertical transistor includes a storage node, a multiple tunnel junction pattern stacked thereon, a data line stacked thereon, and a word line for covering both sidewalls of the storage node and the multiple tunnel junction pattern. Width of the multiple tunnel junction pattern is narrower than the storage node and data lines. Semiconductor layers and tunnel oxide layers are alternately and repeatedly stacked and anisotropically etched to form the multiple tunnel junction pattern of narrow width while forming the data line and the storage node.

Abstract: A semiconductor memory device and fabricating method thereof, wherein the semiconductor memory device includes first and second conductive regions formed in parallel at predetermined regions of a semiconductor substrate, a storage node and a multiple tunnel junction layer pattern sequentially stacked on a channel region between the first and second conductive regions, a data line stacked on the multiple tunnel junction layer pattern, and a wordline covering both sidewalls of the storage node and of the multiple tunnel junction layer pattern, wherein both sidewalls of the storage node have undercut regions for increasing the overlapping area of the storage node and a wordline. The storage node is formed by alternately and repeatedly stacking first and second conductive layers having different etch rates, successively patterning the conductive layers to form a storage node pattern, and selectively and isotropically etching the first or second conductive layer of the storage node pattern.

Abstract: A semiconductor memory device and fabricating method thereof, wherein the semiconductor memory device includes first and second conductive regions formed in parallel at predetermined regions of a semiconductor substrate, a storage node and a multiple tunnel junction layer pattern sequentially stacked on a channel region between the first and second conductive regions, a data line stacked on the multiple tunnel junction layer pattern, and a wordline covering both sidewalls of the storage node and of the multiple tunnel junction layer pattern, wherein both sidewalls of the storage node have undercut regions for increasing the overlapping area of the storage node and a wordline. The storage node is formed by alternately and repeatedly stacking first and second conductive layers having different etch rates, successively patterning the conductive layers to form a storage node pattern, and selectively and isotropically etching the first or second conductive layer of the storage node pattern.

Abstract: A semiconductor memory device and fabricating method thereof, wherein the semiconductor memory device includes first and second conductive regions formed in parallel at predetermined regions of a semiconductor substrate, a storage node and a multiple tunnel junction layer pattern sequentially stacked on a channel region between the first and second conductive regions, a data line stacked on the multiple tunnel junction layer pattern, and a wordline covering both sidewalls of the storage node and of the multiple tunnel junction layer pattern, wherein both sidewalls of the storage node have undercut regions for increasing the overlapping area of the storage node and a wordline. The storage node is formed by alternately and repeatedly stacking first and second conductive layers having different etch rates, successively patterning the conductive layers to form a storage node pattern, and selectively and isotropically etching the first or second conductive layer of the storage node pattern.

Abstract: The present invention discloses a semiconductor memory device having a multiple tunnel junction pattern and a method of forming the same. The semiconductor memory device includes a unit cell composed of planar transistor and vertical transistors. The planar transistor includes first and second conductive regions formed at predetermined regions of a semiconductor substrate and a storage node stacked on a channel region therebetween. The vertical transistor includes a storage node, a multiple tunnel junction pattern stacked thereon, a data line stacked thereon, and a word line for covering both sidewalls of the storage node and the multiple tunnel junction pattern. Width of the multiple tunnel junction pattern is narrower than the storage node and data lines. Semiconductor layers and tunnel oxide layers are alternately and repeatedly stacked and anisotropically etched to form the multiple tunnel junction pattern of narrow width while forming the data line and the storage node.

Abstract: A semiconductor memory device and fabricating method thereof, wherein the semiconductor memory device includes first and second conductive regions formed in parallel at predetermined regions of a semiconductor substrate, a storage node and a multiple tunnel junction layer pattern sequentially stacked on a channel region between the first and second conductive regions, a data line stacked on the multiple tunnel junction layer pattern, and a wordline covering both sidewalls of the storage node and of the multiple tunnel junction layer pattern, wherein both sidewalls of the storage node have undercut regions for increasing the overlapping area of the storage node and a wordline. The storage node is formed by alternately and repeatedly stacking first and second conductive layers having different etch rates, successively patterning the conductive layers to form a storage node pattern, and selectively and isotropically etching the first or second conductive layer of the storage node pattern.