Abstract: The present application proposes a method and system for quantitative derivation of an on-line evaluation layered model for evaluating concrete dam operation performance, and a storage medium, and relates to the technical field of dam operation safety monitoring and management. A logic architecture of quantitative derivation of the concrete dam operation performance mainly has two aspects, a longitudinal dimension and a transverse dimension. The longitudinal dimension is the principal line of assessing longitudinal evaluation of the on-line evaluation layered model, and an analysis idea of the concrete dam from local to global and from details to whole is objectively reflected from six levels of monitoring data, diagnosis methods, monitored items, evaluation indicators, key parts and an overall project.

Abstract: A beam shaping equipment includes a beam shaping body and a main supporting frame. The beam shaping body includes a front module and a rear module. The rear module defines a working space with the front module therebetween. The working space is configured to accommodate a neutron source. The main supporting frame is configured to support the front module and the rear module. The neutron source is configured to generate a plurality of neutrons. The beam shaping body is configured to adjust an energy spectrum of the neutrons to generate a neutron beam.

Abstract: A heat dissipation structure includes a housing. The housing has opposing upper and lower surfaces, and a fluid channel between the upper surface and the lower surface. The fluid channel is configured to allow a fluid to pass through, and the fluid channel includes an inlet buffer tank, an outlet buffer tank and a connecting structure. The inlet buffer tank has opposing first inner wall and second inner wall surfaces. The outlet buffer tank has opposing first inner wall and second inner wall surfaces, and the second inner wall surface is closer to the inlet buffer tank than the first inner wall surface. The connecting structure is disposed on the inlet buffer tank and the outlet buffer tank, in which the connecting structure has a first bevel surface and a second bevel surface connected to the upper surface of the housing.

Abstract: A heat dissipation system includes a single fan, first and second heat sources, first, second, and third heat pipes, and first and second heat dissipation arrays. The first heat pipe is thermally coupled with the first heat source. The second heat pipe is thermally coupled with the second heat source. The third heat pipe has a first position thermally coupled with the first heat pipe and a second position thermally coupled with the second heat pipe. The first heat dissipation array is arranged around the first position and thermally coupled with the third heat pipe. The second heat dissipation array is arranged around the second position and thermally coupled with the third heat pipe. The single fan is between the first and second heat sources, and configured to blow airflows towards the first and second heat sources, the first and second heat dissipation arrays.

Abstract: A method of fabricating an integrated circuit includes identifying an edge device of a plurality of devices, the plurality of devices being part of a first layout including gate structures and diffusion regions, modifying the first layout resulting in a second layout, and fabricating the integrated circuit based on the second layout. Modifying the first layout resulting in the second layout includes adding a dummy device next to the edge device, the dummy device and the edge device having a shared diffusion region, adding a dummy gate structure next to the dummy device, extending the shared diffusion region to at least the dummy device, and performing a design rule check on the second layout. The performing the design rule check considers a gate structure of the dummy device as one of two dummy gate structures next to the edge device.

Abstract: A heat dissipation system includes a single fan, first and second heat sources, first, second, and third heat pipes, and first and second heat dissipation arrays. The first heat pipe is thermally coupled with the first heat source. The second heat pipe is thermally coupled with the second heat source. The third heat pipe has a first position thermally coupled with the first heat pipe and a second position thermally coupled with the second heat pipe. The first heat dissipation array is arranged around the first position and thermally coupled with the third heat pipe. The second heat dissipation array is arranged around the second position and thermally coupled with the third heat pipe. The single fan is between the first and second heat sources, and configured to blow airflows towards the first and second heat sources, the first and second heat dissipation arrays.

Abstract: A method of fabricating an integrated circuit includes identifying an edge device of a plurality of devices, the plurality of devices being part of a first layout including gate structures and diffusion regions, modifying the first layout resulting in a second layout, and fabricating the integrated circuit based on the second layout. Modifying the first layout resulting in the second layout includes adding a dummy device next to the edge device, the dummy device and the edge device having a shared diffusion region, adding a dummy gate structure next to the dummy device, extending the shared diffusion region to at least the dummy device, and performing a design rule check on the second layout. The performing the design rule check considers a gate structure of the dummy device as one of two dummy gate structures next to the edge device.

Abstract: A method includes designing a first layout of gate structures and diffusion regions of a plurality of active devices, identifying an edge device of the plurality of active devices, modifying the first layout resulting in a second layout, performing a design rule check on the second layout, and fabricating, based on the second layout, at least one of a photolithography mask or at least one component in a layer of a semiconductor device. Modifying the first layout includes adding a dummy device next to the edge device, adding a dummy gate structure next to the dummy device and extending a shared diffusion region to at least the dummy device. The dummy device and the edge device have the shared diffusion region. Performing the design rule check considers a gate structure of the dummy device as one of two dummy gate structures next to the edge device.

Abstract: An electronic device includes a casing wall and a heat dissipation module. The heat dissipation module includes a heat dissipation fin set, a cooling fan, and an isolation layer. The heat dissipation fin set is disposed adjacent to the casing wall, and has a first air inlet and a second air inlet. The heat dissipation fin set includes a plurality of heat dissipation fins. The cooling fan has an air outlet. The air outlet is adjacent to the first air inlet and is spaced from the second air inlet. The isolation layer has at least a part between the first air inlet and the second air inlet.

Abstract: A method includes designing a first layout of gate structures and diffusion regions of a plurality of active devices, identifying an edge device of the plurality of active devices, modifying the first layout resulting in a second layout, performing a design rule check on the second layout, and fabricating, based on the second layout, at least one of a photolithography mask or at least one component in a layer of a semiconductor device. Modifying the first layout includes adding a dummy device next to the edge device, adding a dummy gate structure next to the dummy device and extending a shared diffusion region to at least the dummy device. The dummy device and the edge device have the shared diffusion region. Performing the design rule check considers a gate structure of the dummy device as one of two dummy gate structures next to the edge device.

Abstract: A method includes designing a layout of gate structures and diffusion regions of a plurality of devices, identifying an edge device of the plurality of devices, adding a dummy device next to the edge device and a dummy gate structure next to the dummy device resulting in a modified layout, and fabricating, based on the modified layout, at least one of a photolithography mask or at least one component in a layer of a semiconductor device. The dummy device shares a diffusion region with the edge device. A gate structure of the dummy device is one of two dummy gate structures added next to the edge device.

Abstract: A method includes designing a layout of gate structures and diffusion regions of a plurality of devices, identifying an edge device of the plurality of devices, adding a dummy device next to the edge device and a dummy gate structure next to the dummy device resulting in a modified layout, and fabricating, based on the modified layout, at least one of a photolithography mask or at least one component in a layer of a semiconductor device. The dummy device shares a diffusion region with the edge device. A gate structure of the dummy device is one of two dummy gate structures added next to the edge device.

Abstract: A method of designing a layout of devices includes designing a layout of gate structures and diffusion regions of a plurality of devices. The method further includes identifying an edge device of the plurality of devices. The method further includes adding a dummy device next to the edge device and a dummy gate structure next to the dummy device, wherein the dummy device shares a diffusion region with the edge device, and wherein a gate structure of the dummy device is considered to be one of two dummy gate structures added next to the edge device.

Abstract: Described herein are variant Fc-fragments that contain an insertion within or adjacent to a loop that bind to the neonatal Fc receptor (FcRn) with higher affinity and/or higher binding activity at pH 5-6 and approximately the same or lower affinity at a physiologic pH as compared to a control Fc-fragment, that is, little or no binding activity at a physiologic pH. Also described are variant Fc-polypeptides that comprise these variant Fc-fragments. Further described are methods of making and identifying such Fc-fragments and methods for making and using such Fc-polypeptides.

Abstract: The present invention provides compositions and methods relating to or derived from antigen binding proteins and antigen binding protein-FGF21 fusions that specifically bind to ?-Klotho, or ?-Klotho and one or more of FGFR1c, FGFR2c, FGFR3c, and FGFR4. In some embodiments the antigen binding proteins and antigen binding protein-FGF21 fusions induce FGF21-like signaling. In some embodiments, an antigen binding protein or antigen binding protein-FGF21 fusion antigen binding component is a fully human, humanized, or chimeric antibody, binding fragments and derivatives of such antibodies, and polypeptides that specifically bind to ?-Klotho, or ?-Klotho and one or more of FGFR1c, FGFR2c, FGFR3c, and FGFR4.

Abstract: A circuit includes a first node, a second node, a first current mirror circuit, and a second current mirror circuit. The first current mirror circuit has a reference end and a mirrored end. The reference end of the first current mirror circuit is coupled to the first node, and the mirrored end of the first current mirror circuit is coupled to the second node. The second current mirror circuit has a reference end and a mirrored end. The reference end of the second current mirror circuit is coupled to the second node, and the mirrored end of the second current mirror circuit is coupled to the first node.

Abstract: A battery casing and a battery assembly are disclosed. The battery casing has a casing body, a least one first stress-bearing element, and at least one second stress-bearing element. The casing body has two corresponding disposed first walls and a bearing surface. The at least one first stress-bearing element is disposed on the bearing surface. The two ends of the at least one second stress-bearing element connect with the two first walls and are situated above and aligned with the at least one first stress-hearing element to form at least one stress-bearing space for accommodating at least one battery.

Abstract: Described herein are variant Fc-fragments that contain an insertion within or adjacent to a loop that bind to the neonatal Fc receptor (FcRn) with higher affinity and/or higher binding activity at pH 5-6 and approximately the same or lower affinity at a physiologic pH as compared to a control Fc-fragment, that is, little or no binding activity at a physiologic pH. Also described are variant Fc-polypeptides that comprise these variant Fc-fragments. Further described are methods of making and identifying such Fc-fragments and methods for making and using such Fc-polypeptides.

Abstract: A word line decoder comprises a plurality of driver circuits, a plurality of word lines provided at respective outputs of the driver circuits, and a plurality of primary input lines coupled to the driver circuits and oriented in a first direction. The word line decoder also comprises a plurality of secondary input lines coupled to the driver circuits and oriented in the first direction. The word line decoder also comprises a local decode line coupled to each of the primary input lines. The word line decoder also comprises a decode line coupled to the local decode line and oriented in the first direction. A cluster decode line is coupled to the decode line. The word line decoder is configured to select at least one of the word lines based on signals provided by the cluster decode line and the secondary input lines.

Abstract: A circuit includes a failure address register configured to store a first row address, a row address modifier coupled to the failure address register, wherein the row address modifier is configured to modify the first row address received from the failure address register to generate a second row address. A first comparator is configured to receive and compare the first row address and a third row address. A second comparator is configured to receive and compare the second row address and the third row address. The first and the second row addresses are failed row addresses in a memory.