Abstract: A synapse device, a manufacturing method thereof, and a neuromorphic device including the synapse device are disclosed. The synapse device may include a channel member, a tunnel insulating layer disposed on the channel member, a charge trap layer disposed on the tunnel insulating layer, a blocking insulating layer disposed on the charge trap layer, a gate electrode disposed on the blocking insulating layer, a first terminal and a second terminal respectively connected to first and second regions of the channel member, and first and second conductors respectively bonded to the first and second terminals The charge trap layer may have a multilayer structure including a first trap layer disposed adjacent to the channel member and a second trap layer disposed adjacent to the gate electrode. The first trap layer may have a trap of a shallower level than that of the second trap layer.

Abstract: A semiconductor device includes a first and second active pattern extending in a first direction on a substrate, a first and second gate electrode extending in a second direction to intersect the first and second active pattern, a first source/drain contact extending in the second direction and connected to a first and source/drain region of the first and second active patterns, respectively, a first source/drain via connected to the first source/drain contact, a first cell separation film extending in the second direction and crosses the first active pattern and the second active pattern, between the first source/drain contact and the second gate electrode, a first gate via connected to the second gate electrode and arranged with the first source/drain via along the first direction, and a first connection wiring which extending in the first direction and connects the first source/drain via and the first gate via.

Abstract: A synaptic device, a neuromorphic device including the synaptic device, and operating methods thereof are disclosed. A synaptic device may comprise a channel, a charge trap layer directly contacting the channel, a blocking insulating layer disposed on the charge trap layer, a control electrode disposed on the blocking insulating layer, a first terminal connected to a first region of the channel, and a second terminal connected to a second region of the channel. The synaptic device may change a post-synaptic current (PSC) and control synaptic plasticity according to a control signal applied to the control electrode. The synaptic device may have a SONS (doped poly-silicon/blocking oxide/charge trap nitride/silicon channel) structure. The synaptic device may have SADP characteristics, SDDP characteristics, SFDP characteristics, SNDP characteristics, and STDP characteristics.

Abstract: A nonvolatile memory device and an operating method thereof are disclosed. An operating method of a nonvolatile memory device may comprise providing the nonvolatile memory device including a memory transistor, the memory transistor including a source, a drain, a channel disposed between the source and the drain, and a first insulating layer, a charge storage layer, a second insulating layer, and a gate which are sequentially disposed on the channel, and curing the memory transistor by removing charges or traps existing at least at an interface between the channel and the first insulating layer by generating a gate induced drain leakage (GIDL) current on the drain side of the memory transistor and using Joule heating caused by the GIDL current.

Abstract: Disclosed is an ion controllable transistor-based neuromorphic synaptic device used for a memory and a neuromorphic computing in such a manner that a synaptic weight is analogically updated and maintained. The ion controllable transistor-based neuromorphic synaptic device includes a channel area formed on a semiconductor substrate; a source area and a drain area formed at both sides of the channel area, respectively; an interlayer insulating film provided on the channel area; a gate area formed on the interlayer insulating film; and a solid electrolyte layer inserted between the interlayer insulating film and the gate area.