Patents by Inventor Ji-Min LIN
Ji-Min LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11683060Abstract: A radio frequency circuit with font routing to replace a resistor includes a routing layer and a ground layer. The routing layer includes a first pad, a second pad and a font routing unit. The second pad is corresponding to the first pad. The font routing unit is connected between the first pad and the second pad, and has a trace width. The trace width is less than a 50 ohm trace width. The ground layer is disposed below the routing layer and is separated from the routing layer by a height. The font routing unit has a second equivalent impedance at the radio frequency, the second equivalent impedance is determined according to the trace width, the height and the radio frequency, and the second equivalent impedance is the same or similar to a first equivalent impedance.Type: GrantFiled: January 25, 2022Date of Patent: June 20, 2023Assignee: USI Science and Technology (Shenzhen) Co., Ltd.Inventors: Wen-Shuo Liu, Ji-Min Lin, Syuan-Ci Lin, Yu-An Hsieh
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Publication number: 20230126592Abstract: A radio frequency circuit with font routing to replace a resistor includes a routing layer and a ground layer. The routing layer includes a first pad, a second pad and a font routing unit. The second pad is corresponding to the first pad. The font routing unit is connected between the first pad and the second pad, and has a trace width. The trace width is less than a 50 ohm trace width. The ground layer is disposed below the routing layer and is separated from the routing layer by a height. The font routing unit has a second equivalent impedance at the radio frequency, the second equivalent impedance is determined according to the trace width, the height and the radio frequency, and the second equivalent impedance is the same or similar to a first equivalent impedance.Type: ApplicationFiled: January 25, 2022Publication date: April 27, 2023Inventors: WEN-SHUO LIU, Ji-Min Lin, Syuan-CI Lin, Yu-An Hsieh
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Patent number: 11599702Abstract: An excitation source planning method for an electrical stimulation is proposed to plan an excitation source. A layout importing step is performed to drive a processing unit to import a PCB layout to an electromagnetic simulation software module. A port establishing step is performed to set the excitation source to be vertically disposed between a signal layer and a main ground layer. A model generating step is performed to perform the electrical simulation according to the excitation source to generate a three-dimensional simulation model corresponding to the PCB layout. When the signal layer is not electrically connected to the main ground layer, the electromagnetic simulation software module executes an extending step. The extending step is performed to provide a first metal unit to be connected to the signal layer, and reset the excitation source to be vertically disposed between the first metal unit and the main ground layer.Type: GrantFiled: April 15, 2021Date of Patent: March 7, 2023Assignee: Universal Scientific Industrial (Shanghai) Co., Ltd.Inventors: Wei-Yuan Lin, Ji-Min Lin
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Publication number: 20220253585Abstract: An excitation source planning method for an electrical stimulation is proposed to plan an excitation source. A layout importing step is performed to drive a processing unit to import a PCB layout to an electromagnetic simulation software module. A port establishing step is performed to set the excitation source to be vertically disposed between a signal layer and a main ground layer. A model generating step is performed to perform the electrical simulation according to the excitation source to generate a three-dimensional simulation model corresponding to the PCB layout. When the signal layer is not electrically connected to the main ground layer, the electromagnetic simulation software module executes an extending step. The extending step is performed to provide a first metal unit to be connected to the signal layer, and reset the excitation source to be vertically disposed between the first metal unit and the main ground layer.Type: ApplicationFiled: April 15, 2021Publication date: August 11, 2022Inventors: Wei-Yuan LIN, Ji-Min LIN
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Publication number: 20220084878Abstract: A fabricating method of transistors includes providing a substrate with numerous transistors thereon. Each of the transistors includes a gate structure. A gap is disposed between gate structures adjacent to each other. Later, a protective layer and a first dielectric layer are formed in sequence to cover the substrate and the transistors and to fill in the gap. Next, numerous buffering particles are formed to contact the first dielectric layer. The buffering particles do not contact each other. Subsequently, a second dielectric layer is formed to cover the buffering particles. After that, a first planarization process is performed to remove part of the first dielectric layer, part of the second dielectric layer and buffering particles by taking the protective layer as a stop layer, wherein a removing rate of the second dielectric layer is greater than a removing rate of the buffering particles during the first planarization process.Type: ApplicationFiled: September 17, 2020Publication date: March 17, 2022Inventors: Fu-Shou Tsai, Yang-Ju Lu, Yong-Yi Lin, Yu-Lung Shih, Ching-Yang Chuang, Ji-Min Lin, Kun-Ju Li
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Patent number: 11257711Abstract: A fabricating method of transistors includes providing a substrate with numerous transistors thereon. Each of the transistors includes a gate structure. A gap is disposed between gate structures adjacent to each other. Later, a protective layer and a first dielectric layer are formed in sequence to cover the substrate and the transistors and to fill in the gap. Next, numerous buffering particles are formed to contact the first dielectric layer. The buffering particles do not contact each other. Subsequently, a second dielectric layer is formed to cover the buffering particles. After that, a first planarization process is performed to remove part of the first dielectric layer, part of the second dielectric layer and buffering particles by taking the protective layer as a stop layer, wherein a removing rate of the second dielectric layer is greater than a removing rate of the buffering particles during the first planarization process.Type: GrantFiled: September 17, 2020Date of Patent: February 22, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Fu-Shou Tsai, Yang-Ju Lu, Yong-Yi Lin, Yu-Lung Shih, Ching-Yang Chuang, Ji-Min Lin, Kun-Ju Li
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Patent number: 11222784Abstract: A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a silicon layer on the substrate, a titanium nitride (TiN) layer on the silicon layer, a titanium (Ti) layer between the TiN layer and the silicon layer, a metal silicide between the Ti layer and the silicon layer, a titanium silicon nitride (TiSiN) layer on the TiN layer, and a conductive layer on the TiSiN layer.Type: GrantFiled: March 27, 2020Date of Patent: January 11, 2022Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Tzu-Hao Liu, Yi-Wei Chen, Tsun-Min Cheng, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Po-Chih Wu, Pin-Hong Chen, Chun-Chieh Chiu, Tzu-Chieh Chen, Chih-Chien Liu, Chih-Chieh Tsai, Ji-Min Lin
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Patent number: 11211471Abstract: The present invention discloses a metal gate process. A sacrificial nitride layer is introduced during the fabrication of metal gates. The gate height can be well controlled by introducing the sacrificial nitride layer. Further, the particle fall-on problem can be effectively solved.Type: GrantFiled: September 10, 2020Date of Patent: December 28, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Fu-Shou Tsai, Yong-Yi Lin, Yang-Ju Lu, Yu-Lung Shih, Ji-Min Lin, Ching-Yang Chuang, Kun-Ju Li
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Patent number: 11145602Abstract: An alignment mark structure includes a dielectric layer. A trench is embedded in the dielectric layer. An alignment mark fills up the trench, wherein the alignment mark includes a metal layer covering the trench. A first material layer covers and contacts the metal layer. A second material layer covers and contacts the first material layer. A third material layer covers and contacts the second material layer. The first material layer, the second material layer, and the third material layer independently includes silicon nitride, silicon oxide, tantalum-containing material, aluminum-containing material, titanium-containing material, or a low-k dielectric having a dielectric constant smaller than 2.7, and a reflectance of the first material layer is larger than a reflectance of the second material layer, the reflectance of the second material layer is larger than a reflectance of the third material layer.Type: GrantFiled: February 10, 2020Date of Patent: October 12, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kun-Ju Li, Jhih-Yuan Chen, Hsin-Jung Liu, Chau-Chung Hou, Yu-Lung Shih, Ang Chan, Fu-Chun Hsiao, Ji-Min Lin, Chun-Han Chen
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Publication number: 20210249357Abstract: An alignment mark structure includes a dielectric layer. A trench is embedded in the dielectric layer. An alignment mark fills up the trench, wherein the alignment mark includes a metal layer covering the trench. A first material layer covers and contacts the metal layer. A second material layer covers and contacts the first material layer. A third material layer covers and contacts the second material layer. The first material layer, the second material layer, and the third material layer are independently comprises silicon nitride, silicon oxide, tantalum-containing material, aluminum-containing material, titanium-containing material, or a low-k dielectric having a dielectric constant smaller than 2.7, and a reflectance of the first material layer is larger than a reflectance of the second material layer, the reflectance of the second material layer is larger than a reflectance of the third material layer.Type: ApplicationFiled: February 10, 2020Publication date: August 12, 2021Inventors: Kun-Ju Li, Jhih-Yuan Chen, Hsin-Jung Liu, Chau-Chung Hou, Yu-Lung Shih, Ang Chan, Fu-Chun Hsiao, Ji-Min Lin, Chun-Han Chen
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Publication number: 20200227264Abstract: A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a silicon layer on the substrate, a titanium nitride (TiN) layer on the silicon layer, a titanium (Ti) layer between the TiN layer and the silicon layer, a metal silicide between the Ti layer and the silicon layer, a titanium silicon nitride (TiSiN) layer on the TiN layer, and a conductive layer on the TiSiN layer.Type: ApplicationFiled: March 27, 2020Publication date: July 16, 2020Inventors: Tzu-Hao Liu, Yi-Wei Chen, Tsun-Min Cheng, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Po-Chih Wu, Pin-Hong Chen, Chun-Chieh Chiu, Tzu-Chieh Chen, Chih-Chien Liu, Chih-Chieh Tsai, Ji-Min Lin
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Patent number: 10651040Abstract: A method for fabricating semiconductor device includes the steps of: forming a titanium nitride (TiN) layer on a silicon layer; performing a first treatment process by reacting the TiN layer with dichlorosilane (DCS) to form a titanium silicon nitride (TiSiN) layer; forming a conductive layer on the TiSiN layer; and patterning the conductive layer, the metal silicon nitride layer, and the silicon layer to form a gate structure.Type: GrantFiled: May 22, 2018Date of Patent: May 12, 2020Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Tzu-Hao Liu, Yi-Wei Chen, Tsun-Min Cheng, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Po-Chih Wu, Pin-Hong Chen, Chun-Chieh Chiu, Tzu-Chieh Chen, Chih-Chien Liu, Chih-Chieh Tsai, Ji-Min Lin
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Publication number: 20190318933Abstract: A method for fabricating semiconductor device includes the steps of: forming a titanium nitride (TiN) layer on a silicon layer; performing a first treatment process by reacting the TiN layer with dichlorosilane (DCS) to form a titanium silicon nitride (TiSiN) layer; forming a conductive layer on the TiSiN layer; and patterning the conductive layer, the metal silicon nitride layer, and the silicon layer to form a gate structure.Type: ApplicationFiled: May 22, 2018Publication date: October 17, 2019Inventors: Tzu-Hao Liu, Yi-Wei Chen, Tsun-Min Cheng, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Po-Chih Wu, Pin-Hong Chen, Chun-Chieh Chiu, Tzu-Chieh Chen, Chih-Chien Liu, Chih-Chieh Tsai, Ji-Min Lin
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Patent number: 10373916Abstract: A semiconductor device package includes a substrate, a component on a surface of the substrate, a package body encapsulating the component, and an electromagnetic interference (EMI) shield conformally formed on the package body, where the EMI shield has a side portion defining an opening.Type: GrantFiled: July 28, 2016Date of Patent: August 6, 2019Assignee: UNIVERSAL SCIENTIFIC INDUSTRIAL (SHANGHAI) CO., LTD.Inventors: Ji-Min Lin, Ming-Wen Liao, Chun-Ying Huang
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Patent number: 10374051Abstract: A method for fabricating semiconductor device includes the steps of: forming a silicon layer on a substrate; forming a metal silicon nitride layer on the silicon layer; forming a stress layer on the metal silicon nitride layer; performing a thermal treatment process; removing the stress layer; forming a conductive layer on the metal silicon nitride layer; and patterning the conductive layer, the metal silicon nitride layer, and the silicon layer to form a gate structure.Type: GrantFiled: May 23, 2018Date of Patent: August 6, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Ji-Min Lin, Yi-Wei Chen, Tsun-Min Cheng, Pin-Hong Chen, Chih-Chien Liu, Chun-Chieh Chiu, Tzu-Chieh Chen, Chih-Chieh Tsai, Yi-An Huang, Kai-Jiun Chang
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Publication number: 20180033736Abstract: A semiconductor device package includes a substrate, a component on a surface of the substrate, a package body encapsulating the component, and an electromagnetic interference (EMI) shield conformally formed on the package body, where the EMI shield has a side portion defining an opening.Type: ApplicationFiled: July 28, 2016Publication date: February 1, 2018Inventors: Ji-Min LIN, Ming-Wen Liao, Chun-Ying Huang