Patents by Inventor Ji-Myoung Lee
Ji-Myoung Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11948808Abstract: A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide a method for manufacturing a semiconductor device, and a semiconductor device produced thereby, that comprises an interposer without through silicon vias.Type: GrantFiled: December 6, 2021Date of Patent: April 2, 2024Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.Inventors: Dong Jin Kim, Jin Han Kim, Won Chul Do, Jae Hun Bae, Won Myoung Ki, Dong Hoon Han, Do Hyung Kim, Ji Hun Lee, Jun Hwan Park, Seung Nam Son, Hyun Cho, Curtis Zwenger
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Patent number: 11918531Abstract: Provided is a thermotherapy device, which includes a first housing (10), a second housing (20) disposed under the first housing (10), a transfer plate (30), at both sides of which transfer rollers (31) are provided, and a pair of guide rails (40) that is provided to the second housing (20) and on which the respective transfer rollers (31) of the transfer plate (30) are placed. The pair of guide rails (40) are integrally molded when the second housing (20) is injection-molded. Thus, since the guide rails on which the transfer rollers of the transfer plate travel are integrally molded when the second housing is injection-molded, inefficiency caused by mounting separate rails as in the related art is removed, and thereby assemblability, productivity, and economic efficiency of the thermotherapy device can be improved.Type: GrantFiled: February 26, 2020Date of Patent: March 5, 2024Assignee: Ceragem Co., Ltd.Inventors: Dong Myoung Lee, Sang Min Lee, Ho Sang Yu, Ji Hoon Park, Sang Ui Choi
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Publication number: 20230337366Abstract: A circuit board according to an embodiment includes an insulating layer; a protective layer disposed on the insulating layer and including an opening; and a circuit pattern disposed on an insulating layer vertically overlapping the opening of the protective layer, wherein the circuit pattern includes: a first metal layer disposed on an upper surface of the insulating layer vertically overlapping the opening of the protective layer; a second metal layer disposed on the first metal layer; and a third metal layer disposed on the second metal layer, wherein the second metal layer includes: a first portion disposed between an upper surface of the first metal layer and a lower surface of the third metal layer; and a second portion disposed between an inner wall of the opening of the protective layer and a side surface of the third metal layer.Type: ApplicationFiled: September 10, 2021Publication date: October 19, 2023Applicant: LG INNOTEK CO., LTD.Inventor: Ji Myoung LEE
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Patent number: 10276349Abstract: A plasma processing device is provided. The plasma processing device includes a plate formed between a window covering a top portion of a chamber where plasma processing is performed and an antenna generating a magnetic field, and a fluid supply unit supplying a fluid for controlling temperatures of the window and the antenna, wherein the plate includes first and second regions supplied with the fluid, and the fluid supply unit independently controls the first and second regions.Type: GrantFiled: April 29, 2015Date of Patent: April 30, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Hak-Young Kim, Ji-Myoung Lee, Ji-Hee Kim, Doug-Yong Sung, Kyeong-Seok Jeong, Seong-Chul Choi
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Patent number: 10153277Abstract: An integrated circuit device includes: a pair of width-setting patterns over a substrate, the pair of width-setting patterns defining a width of a gate structure space in a first direction and extending in a second direction intersecting with the first direction. A gate electrode layer is provided that extends in the gate structure space along the second direction. A gate insulating layer is provided in the gate structure space and between the substrate and the gate electrode layer. An insulating spacer is provides on the pair of width-setting patterns, the insulating spacer covering both sidewalls of the gate electrode layer, wherein the pair of width-setting patterns have a carbon content that is greater than a carbon content of the insulating spacer.Type: GrantFiled: December 23, 2016Date of Patent: December 11, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong-suk Tak, Tae-jong Lee, Gi-gwan Park, Ji-myoung Lee
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Publication number: 20170221893Abstract: An integrated circuit device includes: a pair of width-setting patterns over a substrate, the pair of width-setting patterns defining a width of a gate structure space in a first direction and extending in a second direction intersecting with the first direction. A gate electrode layer is provided that extends in the gate structure space along the second direction. A gate insulating layer is provided in the gate structure space and between the substrate and the gate electrode layer. An insulating spacer is provides on the pair of width-setting patterns, the insulating spacer covering both sidewalls of the gate electrode layer, wherein the pair of width-setting patterns have a carbon content that is greater than a carbon content of the insulating spacer.Type: ApplicationFiled: December 23, 2016Publication date: August 3, 2017Inventors: Yong-suk TAK, Tae-jong LEE, Gi-gwan PARK, Ji-myoung LEE
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Patent number: 9318477Abstract: A semiconductor device is disclosed. The semiconductor device includes a plurality of dummy gate lines parallel to each other in a first direction and extending in a second direction that is orthogonal to the first direction; a plurality of first dummy filling patterns between the plurality of dummy gate lines, the first dummy filling patterns parallel to each other in the first direction, and arranged apart from each other in the second direction; a plurality of first dummy vias on the plurality of first dummy filling patterns; and a plurality of first dummy wiring lines connected to the plurality of first dummy vias, the first dummy vias extending in the second direction, and parallel to each other in the first direction.Type: GrantFiled: September 23, 2014Date of Patent: April 19, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-myoung Lee, Young-soo Song, Bo-young Lee, Jun-min Lee
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Publication number: 20160104604Abstract: A plasma processing device is provided. The plasma processing device includes a plate formed between a window covering a top portion of a chamber where plasma processing is performed and an antenna generating a magnetic field, and a fluid supply unit supplying a fluid for controlling temperatures of the window and the antenna, wherein the plate includes first and second regions supplied with the fluid, and the fluid supply unit independently controls the first and second regions.Type: ApplicationFiled: April 29, 2015Publication date: April 14, 2016Inventors: Hak-Young Kim, Ji-Myoung Lee, Ji-Hee Kim, Doug-Yong Sung, Kyeong-Seok Jeong, Seong-Chul Choi
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Patent number: 9105467Abstract: A semiconductor device includes a substrate; a device area of the substrate, the device area including a plurality of device unit cells; and a dummy cell array arranged around the device area. The dummy cell array includes a plurality of dummy unit cells repeatedly arranged in a first direction and a second direction perpendicular to the first direction, each of the dummy cell unit having a structure corresponding to a device unit cell. The device unit cell includes at least a first transistor in the device area. The structure of the dummy unit cell includes an active area and a gate line. For each dummy unit cell, the active area and the gate line extend beyond a cell boundary that defines the dummy unit cell.Type: GrantFiled: September 16, 2014Date of Patent: August 11, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-Myoung Lee, Young-Soo Song, Jun-Min Lee, Bo-Young Lee
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Publication number: 20150091188Abstract: A semiconductor device is disclosed. The semiconductor device includes a plurality of dummy gate lines parallel to each other in a first direction and extending in a second direction that is orthogonal to the first direction; a plurality of first dummy filling patterns between the plurality of dummy gate lines, the first dummy filling patterns parallel to each other in the first direction, and arranged apart from each other in the second direction; a plurality of first dummy vias on the plurality of first dummy filling patterns; and a plurality of first dummy wiring lines connected to the plurality of first dummy vias, the first dummy vias extending in the second direction, and parallel to each other in the first direction.Type: ApplicationFiled: September 23, 2014Publication date: April 2, 2015Inventors: Ji-myoung Lee, Young-soo Song, Bo-young Lee, Jun-min Lee
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Publication number: 20150084129Abstract: A semiconductor device includes a substrate; a device area of the substrate, the device area including a plurality of device unit cells; and a dummy cell array arranged around the device area. The dummy cell array includes a plurality of dummy unit cells repeatedly arranged in a first direction and a second direction perpendicular to the first direction, each of the dummy cell unit having a structure corresponding to a device unit cell. The device unit cell includes at least a first transistor in the device area. The structure of the dummy unit cell includes an active area and a gate line. For each dummy unit cell, the active area and the gate line extend beyond a cell boundary that defines the dummy unit cell.Type: ApplicationFiled: September 16, 2014Publication date: March 26, 2015Inventors: Ji-Myoung LEE, Young-Soo SONG, Jun-Min LEE, Bo-Young LEE
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Patent number: 8525147Abstract: A semiconductor device that may control a formation of a channel is disclosed. The semiconductor device includes a gate region including a first area, an insulating layer disposed on portions of a top surface of the gate region corresponding to both ends portions of the first area, first and second electrodes formed on the insulating layer to be spaced apart from each other, an elastic conductive layer disposed between the first and second electrodes and the insulating layer and having a shape that varies according to an electrostatic force based on voltages applied to the first electrode, the second electrode, and the gate region, and a gate insulating region disposed between the elastic conductive layer and the first area of the gate region.Type: GrantFiled: April 19, 2011Date of Patent: September 3, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-myoung Lee, Min-sang Kim, Dong-won Kim
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Patent number: 8391057Abstract: A memory device includes a memory cell that includes a storage node, a first electrode, and a second electrode, the storage node stores an electrical charge, and the first electrode moves to connect to the storage node when the second electrode is energized.Type: GrantFiled: July 31, 2009Date of Patent: March 5, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Min-Sang Kim, Ji-Myoung Lee, Hyun-Jun Bae, Dong-Won Kim, Jun Seo, Yong-Hyun Kwon, Weon-Wi Jang, Keun-Hwi Cho
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Patent number: 8270211Abstract: A memory device includes a storage node, a first electrode, and a second electrode formed in a memory cell, the storage node stores electrical charges, the first electrode comprising a first portion electrically connected to a second portion, the first portion moves to connect to the storage node when the second electrode is energized.Type: GrantFiled: April 8, 2011Date of Patent: September 18, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Min-Sang Kim, Ji-Myoung Lee, Hyun-Jun Bae, Dong-Won Kim, Jun Seo, Weonwi Jang, Keun-Hwi Cho
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Patent number: 8222067Abstract: A multibit electro-mechanical memory device comprises a substrate, a bit line on the substrate, a first interlayer insulating film on the bit line, first and second lower word lines on the first interlayer insulating film, the first and second lower word lines separated horizontally from each other by a trench, a spacer abutting a sidewall of each of the first and second lower word lines, a pad electrode inside a contact hole, first and second cantilever electrodes suspended over first and second lower voids that correspond to upper parts of the first and second lower word lines provided in both sides on the pad electrode, the first and second cantilever electrodes being separated from each other by the trench, and being curved in a third direction that is perpendicular to the first and second direction; a second interlayer insulating film on the pad electrode, first and second trap sites supported by the second interlayer insulating film to have first and second upper voids on the first and second cantileverType: GrantFiled: May 26, 2011Date of Patent: July 17, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-Jung Yun, Min-Sang Kim, Sung-Min Kim, Sung-Young Lee, Ji-Myoung Lee, In-Hyuk Choi
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Patent number: 8106464Abstract: A semiconductor device having a bar type active pattern and a method of manufacturing the same are provided. The semiconductor device may include a semiconductor substrate having a semiconductor fin configured to protrude from a surface of the semiconductor substrate in a first direction, the semiconductor substrate having a first width and a second width crossing the first width, wherein the first width and the second width extend in a second direction. A plurality of active patterns may be arranged in the first direction with a separation gap from the semiconductor fin. A plurality of support patterns may be arranged between the semiconductor fin and one of the plurality of active patterns arranged closer to the semiconductor fin in the first direction, and between the plurality of active patterns arranged in the first direction to support the plurality of active patterns.Type: GrantFiled: August 13, 2009Date of Patent: January 31, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Keun-hwl Cho, Dong-won Kim, Jun Seo, Min-sang Kim, Sung-min Kim, Hyun-jun Bae, Ji-Myoung Lee
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Publication number: 20110260136Abstract: A semiconductor device that may control a formation of a channel is disclosed. The semiconductor device includes a gate region including a first area, an insulating layer disposed on portions of a top surface of the gate region corresponding to both ends portions of the first area, first and second electrodes formed on the insulating layer to be spaced apart from each other, an elastic conductive layer disposed between the first and second electrodes and the insulating layer and having a shape that varies according to an electrostatic force based on voltages applied to the first electrode, the second electrode, and the gate region, and a gate insulating region disposed between the elastic conductive layer and the first area of the gate region.Type: ApplicationFiled: April 19, 2011Publication date: October 27, 2011Inventors: Ji-myoung Lee, Min-sang Kim, Dong-won Kim
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Publication number: 20110230001Abstract: A multibit electro-mechanical memory device comprises a substrate, a bit line on the substrate, a first interlayer insulating film on the bit line, first and second lower word lines on the first interlayer insulating film, the first and second lower word lines separated horizontally from each other by a trench, a spacer abutting a sidewall of each of the first and second lower word lines, a pad electrode inside a contact hole, first and second cantilever electrodes suspended over first and second lower voids that correspond to upper parts of the first and second lower word lines provided in both sides on the pad electrode, the first and second cantilever electrodes being separated from each other by the trench, and being curved in a third direction that is perpendicular to the first and second direction; a second interlayer insulating film on the pad electrode, first and second trap sites supported by the second interlayer insulating film to have first and second upper voids on the first and second cantileverType: ApplicationFiled: May 26, 2011Publication date: September 22, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eun-Jung Yun, Min-Sang Kim, Sung-Min Kim, Sung-Young Lee, Ji-Myoung Lee, In-Hyuk Choi
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Publication number: 20110182111Abstract: A memory device includes a storage node, a first electrode, and a second electrode formed in a memory cell, the storage node stores electrical charges, the first electrode comprising a first portion electrically connected to a second portion, the first portion moves to connect to the storage node when the second electrode is energized.Type: ApplicationFiled: April 8, 2011Publication date: July 28, 2011Inventors: Min-Sang Kim, Ji-Myoung Lee, Hyun-Jun Bae, Dong-Won Kim, Jun Seo, Weonwi Jang, Keun-Hwi Cho
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Patent number: 7973343Abstract: A multibit electro-mechanical memory device comprises a substrate, a bit line on the substrate, a first interlayer insulating film on the bit line, first and second lower word lines on the first interlayer insulating film, the first and second lower word lines separated horizontally from each other by a trench, a spacer abutting a sidewall of each of the first and second lower word lines, a pad electrode inside a contact hole, first and second cantilever electrodes suspended over first and second lower voids that correspond to upper parts of the first and second lower word lines provided in both sides on the pad electrode, the first and second cantilever electrodes being separated from each other by the trench, and being curved in a third direction that is perpendicular to the first and second direction; a second interlayer insulating film on the pad electrode, first and second trap sites supported by the second interlayer insulating film to have first and second upper voids on the first and second cantileverType: GrantFiled: May 23, 2008Date of Patent: July 5, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-Jung Yun, Min-Sang Kim, Sung-Min Kim, Sung-Young Lee, Ji-Myoung Lee, In-Hyuk Choi