Patents by Inventor Ji-Quan Liu
Ji-Quan Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11191705Abstract: Cleansing compositions can include hinokitiol; and a 2-pyridinol N-oxide material; wherein the ratio by weight of the 2-pyridinol N-oxide material to the hinokitiol is about 1:4 to about 2:1 and the combination of the 2-pyridinol N-oxide material and hinokitiol includes about 9 ppm or more by weight of the cleansing composition.Type: GrantFiled: September 10, 2018Date of Patent: December 7, 2021Assignee: The Procter and Gamble CompanyInventors: Huan Wang, Ji-Quan Liu, Nadine Susanne Gallitschke-Irvine
-
Patent number: 10707134Abstract: FinFET structures and fabrication methods thereof are provided. An exemplary fabrication method includes forming a semiconductor substrate and a plurality of fins. First trenches and second trenches are formed between adjacent fins, and a width of the first trench is greater than a width of the second trench. The method also includes forming a first isolation layer on the semiconductor substrate exposed by the fins and on side surfaces of the fins. The first isolation layer containing an opening at the first trench. Further, the method also includes performing a first thermal annealing; forming a second isolation layer to fill the opening; removing a partial thickness of the first isolation layer and a partial thickness of the second layer to form an isolation structure; forming a gate structure across the plurality of fins; and forming doped source/drain regions in the fins at two sides of the gate structure.Type: GrantFiled: November 13, 2017Date of Patent: July 7, 2020Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventor: Ji Quan Liu
-
Publication number: 20200078281Abstract: Cleansing compositions can include hinokitiol; and a 2-pyridinol N-oxide material; wherein the ratio by weight of the 2-pyridinol N-oxide material to the hinokitiol is about 1:4 to about 2:1 and the combination of the 2-pyridinol N-oxide material and hinokitiol includes about 9 ppm or more by weight of the cleansing composition.Type: ApplicationFiled: September 10, 2018Publication date: March 12, 2020Inventors: Huan WANG, Ji-Quan LIU, Nadine Susanne GALLITSCHKE-IRVINE
-
Patent number: 10424599Abstract: Semiconductor structures are provided. A semiconductor structure includes a bottom substrate having a first region and a second region; an insulation layer formed on the bottom substrate in the first region; a top substrate on side surface of the trench and the insulation layer; a first fin portion formed over the insulation layer, and a gate structure crossing the first fin portion. The first fin portion is electrically isolated from the bottom substrate through the insulation layer to reduce the leakage current at the bottom of the first fin portion. The gate structure covers part of side and top surfaces of the first fin portion.Type: GrantFiled: February 13, 2018Date of Patent: September 24, 2019Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Ji Quan Liu, Chun Lei Gong
-
Publication number: 20180374755Abstract: FinFET structures and fabrication methods thereof are provided. An exemplary fabrication method includes forming a semiconductor substrate and a plurality of fins. First trenches and second trenches are formed between adjacent fins, and a width of the first trench is greater than a width of the second trench. The method also includes forming a first isolation layer on the semiconductor substrate exposed by the fins and on side surfaces of the fins. The first isolation layer containing an opening at the first trench. Further, the method also includes performing a first thermal annealing; forming a second isolation layer to fill the opening; removing a partial thickness of the first isolation layer and a partial thickness of the second layer to form an isolation structure; forming a gate structure across the plurality of fins; and forming doped source/drain regions in the fins at two sides of the gate structure.Type: ApplicationFiled: November 13, 2017Publication date: December 27, 2018Applicant: Semiconductor Manufacturing International (Beijing) CorporationInventor: Ji Quan LIU
-
Publication number: 20180175068Abstract: Semiconductor structures are provided. A semiconductor structure includes a bottom substrate having a first region and a second region; an insulation layer formed on the bottom substrate in the first region; a top substrate on side surface of the trench and the insulation layer; a first fin portion formed over the insulation layer, and a gate structure crossing the first fin portion. The first fin portion is electrically isolated from the bottom substrate through the insulation layer to reduce the leakage current at the bottom of the first fin portion. The gate structure covers part of side and top surfaces of the first fin portion.Type: ApplicationFiled: February 13, 2018Publication date: June 21, 2018Inventors: Ji Quan LIU, Chun Lei GONG
-
Publication number: 20180144987Abstract: FinFET structures and fabrication methods thereof are provided. An exemplary fabrication method includes forming a semiconductor substrate and a plurality of fins. First trenches and second trenches are formed between adjacent fins, and a width of the first trench is greater than a width of the second trench. The method also includes forming a first isolation layer on the semiconductor substrate exposed by the fins and on side surfaces of the fins. The first isolation layer containing an opening at the first trench. Further, the method also includes performing a first thermal annealing; forming a second isolation layer to fill the opening; removing a partial thickness of the first isolation layer and a partial thickness of the second layer to form an isolation structure; forming a gate structure across the plurality of fins; and forming doped source/drain regions in the fins at two sides of the gate structure.Type: ApplicationFiled: November 13, 2017Publication date: May 24, 2018Applicant: Semiconductor Manufacturing International (Beijing) CorporationInventor: Ji Quan LIU
-
Patent number: 9978677Abstract: In some embodiments, a contact via and a fabricating method thereof are provided. The method can comprise: providing a substrate; forming a buffer layer in the substrate; forming a dielectric layer covering the substrate and the buffer layer; forming a through hole in the dielectric layer, wherein a bottom of the through hole exposes a surface of the buffer layer; performing a roughening treatment to the exposed surface of the buffer layer to increase a roughness of the exposed surface of the buffer layer; forming a barrier layer in the through hole, and reducing a thickness of a portion of the barrier layer at the bottom of the through hole; and filling a conductive material into the through hole to form a contact via.Type: GrantFiled: October 25, 2016Date of Patent: May 22, 2018Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventor: Ji Quan Liu
-
Patent number: 9929182Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a bottom substrate having a first region and a second region, and forming a trench in the first region by patterning the bottom substrate. The method also includes forming an insulation layer in the trench in the first region, wherein the insulation layer exposes part of side surface of the trench, and forming a top substrate on the exposed side surface of the trench and the insulation layer. Further, the method includes forming a first fin portion in the first region, and forming a gate structure crossing the first fin portion, wherein the gate structure covers part of side and top surfaces of the first fin portion.Type: GrantFiled: March 8, 2017Date of Patent: March 27, 2018Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: Ji Quan Liu, Chun Lei Gong
-
Publication number: 20170263647Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a bottom substrate having a first region and a second region, and forming a trench in the first region by patterning the bottom substrate. The method also includes forming an insulation layer in the trench in the first region, wherein the insulation layer exposes part of side surface of the trench, and forming a top substrate on the exposed side surface of the trench and the insulation layer. Further, the method includes forming a first fin portion in the first region, and forming a gate structure crossing the first fin portion, wherein the gate structure covers part of side and top surfaces of the first fin portion.Type: ApplicationFiled: March 8, 2017Publication date: September 14, 2017Inventors: Ji Quan LIU, Chun Lei GONG
-
Publication number: 20170117218Abstract: In some embodiments, a contact via and a fabricating method thereof are provided. The method can comprise: providing a substrate; forming a buffer layer in the substrate; forming a dielectric layer covering the substrate and the buffer layer; forming a through hole in the dielectric layer, wherein a bottom of the through hole exposes a surface of the buffer layer; performing a roughening treatment to the exposed surface of the buffer layer to increase a roughness of the exposed surface of the buffer layer; forming a barrier layer in the through hole, and reducing a thickness of a portion of the barrier layer at the bottom of the through hole; and filling a conductive material into the through hole to form a contact via.Type: ApplicationFiled: October 25, 2016Publication date: April 27, 2017Inventor: Ji Quan LIU
-
Patent number: 8129327Abstract: Packaging is provided for high moisture bar soap compositions to address a number of potential problems associated with high moisture bar soap compositions, such as minimizing moisture loss, inhibiting mold growth on paperboard material used in the packaging, and preventing the development of colored stains on the bar soap and packaging resulting from chemical reaction between the high moisture bar soap and the paperboard, especially recycled paperboard. The bar soap packaging comprises a laminate material comprising a paperboard material, a thermoplastic material disposed on at least one side of the paperboard material, and a fungicide.Type: GrantFiled: November 30, 2007Date of Patent: March 6, 2012Assignee: The Procter & Gamble CompanyInventors: Grace (Jing) Zhang, Ji-Quan Liu, Charlie Reyes Salvador
-
Publication number: 20090143267Abstract: Packaging is provided for high moisture bar soap compositions to address a number of potential problems associated with high moisture bar soap compositions, such as minimizing moisture loss, inhibiting mold growth on paperboard material used in the packaging, and preventing the development of colored stains on the bar soap and packaging resulting from chemical reaction between the high moisture bar soap and the paperboard, especially recycled paperboard. The bar soap packaging comprises a laminate material comprising a paperboard material, a thermoplastic material disposed on at least one side of the paperboard material, and a fungicide.Type: ApplicationFiled: November 30, 2007Publication date: June 4, 2009Inventors: Grace (Jing) Zhang, Ji-Quan Liu, Charlie Reyes Salvador