Abstract: Disclosed herein is an earphone module having a speaker capable of reproducing both high- and low-pitched sounds. In an earphone module according to the present invention, two coils and terminal members configured to be electrically connected to the two coils are provided, the two coils and the terminal members are assembled by electrically connecting the two coils and the terminal members to each other, and then the terminal members are connected to an external input circuit through the exposure window of a housing. Accordingly, the manufacturing operation is facilitated and the defect rate is reduced, so that the mass productivity is improved.

Abstract: There is provided an apparatus for forming a magnetic pigment pattern on an article. The apparatus includes: a magnetic pattern mold having nonmagnetic pattern grooves engraved in a predetermined pattern and providing predetermined magnetic field lines on a pattern-forming object surface of an article by generating magnetism in areas outside the nonmagnetic pattern grooves; and a spray unit spraying an adhesive resin composite containing a ferromagnetic pigment onto the pattern-forming object surface of the article. A predetermined magnetic pigment pattern is formed while the magnetic pigment of the adhesive resin composite that is applied to the pattern-forming object surface of the article is rearranged along magnetic field lines generated by the magnetic pattern mold.

Abstract: An electronic price indicator according to an embodiment includes a display displaying product information, an NFC module configured to communicate with a user terminal, a Bluetooth module configured to communicate with the user terminal, and a processor configured to control the display to display the product information received from the user terminal through the Bluetooth module. The processor is further configured to release a sleep mode when receiving an interrupt from the user terminal through the NFC module, and perform Bluetooth communication with the user terminal by initiating a scan for a predetermined period of time to receive an advertising signal from the user terminal.

Abstract: Provided is an image recognition method including the steps of: for a deep learning network that carries out object recognition on a random image, carrying out quantization corresponding to the number of a plurality of different bits to generate a plurality of quantization models respectively corresponding to the number of bits; receiving image data as an input for the deep learning network; determining the uncertainty of the input image data; selecting any one of the plurality of quantization models on the basis of the determined uncertainty; and recognizing an object from the image data by using the selected quantization model, and outputting, as the result of the object recognition, a label corresponding to the image data.

Abstract: A method and an electronic device for translating a speech signal between a first language and a second language with minimized translation delay by translating fewer than all words of the speech signal according to a level of understanding of the second language by a user that receives the translation.

Abstract: A non-volatile memory device includes: a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to selectively control the plurality of word lines, a page buffer including a plurality of latches corresponding to the plurality of bit lines, respectively, and a control circuit configured to control the non-volatile memory device to enter a suspend state after terminating a verify operation of a program loop of a program operation of the plurality of memory cells in response to a suspend request being generated during an execution operation of the program loop.

Abstract: A storage device including, a plurality of non-volatile memories configured to include a memory cell region including at least one first metal pad; and a peripheral circuit region including at least one second metal pad and vertically connected to the memory cell region by the at least one first metal pad and the at least one second metal pad, and a controller connected to the plurality of non-volatile memories through a plurality of channels and configured to control the plurality of non-volatile memories, wherein the controller selects one of a first read operation mode and a second read operation mode and transfers a read command corresponding to the selected read operation mode to the plurality of non-volatile memories, wherein one sensing operation is performed to identify one program state among program sates in the first read operation mode, and wherein at least two sensing operations are performed to identify the one program state among the program states in the second read operation mode.

Abstract: Disclosed is a memory device which includes a memory cell array including memory cells, data latches connected with a sensing node and storing data in a first memory cell of the memory cells, a sensing latch connected with the sensing node, a temporary storage node, a switch connected between the sensing latch and the temporary storage node and configured to operate in response to a temporary storage node setup signal, a first precharge circuit configured to selectively precharge a first bit line corresponding to the first memory cell depending on a level of the temporary storage node, and a control logic circuit configured to control a dump operation between the data latches, the sensing latch, and the temporary storage node. The control logic circuit performs the dump operation from the data latches to the sensing latch while the first precharge circuit selectively precharges the first bit line.

Abstract: A non-volatile memory device includes: a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to selectively control the plurality of word lines, a page buffer including a plurality of latches corresponding to the plurality of bit lines, respectively, and a control circuit configured to control the non-volatile memory device to enter a suspend state after terminating a verify operation of a program loop of a program operation of the plurality of memory cells in response to a suspend request being generated during an execution operation of the program loop.

Abstract: The present invention relates to a method for manufacturing gold nanoparticles, including: (a) placing a gold (Au) target on a magnet cathode and injecting argon (Ar) gas to generate plasma; (b) discharging powder of a compound having an non-shared electron pair upwardly in parallel to a vertical rotation axis inside a stirrer, followed by circulating and agitating the same up and down; and (c) ejecting the gold particles and binding the same to the compound having the non-shared electron pair, as well as gold nanoparticles manufactured by the same. The present invention relates to a method for obtaining gold nanoparticles bound to niacinamide through vacuum deposition, which is generally used to form a thin film, wherein niacinamide is used by circulating and agitating the same up and down under special conditions, so as to produce high purity gold nanoparticles in high yield.

Abstract: A non-volatile memory device includes: a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to selectively control the plurality of word lines, a page buffer including a plurality of latches corresponding to the plurality of bit lines, respectively, and a control circuit configured to control the non-volatile memory device to enter a suspend state after terminating a verify operation of a program loop of a program operation of the plurality of memory cells in response to a suspend request being generated during an execution operation of the program loop.

Abstract: A flash memory device includes a memory cell array connected with word lines and control logic that performs threshold voltage compensation on the word lines through a data recover read operation. When a word line on which programming is performed after a selected word line is a dummy word line, the control logic performs the threshold voltage compensation on the selected word line based on a result of a data recover read operation of a word line on which programming is performed before the selected word line. When a next word line on which programming is performed after a selected word line is a dummy word line, the control logic performs threshold voltage compensation on the selected word line based on a result of performing the data recover read operation on a previous word line on which programming is performed before the selected word line.

Abstract: A nonvolatile memory device includes a memory cell array having cell strings that each includes memory cells stacked on a substrate in a direction perpendicular to the substrate. A row decoder is connected with the memory cells through word lines. The row decoder applies a setting voltage to at least one word line of the word lines and floats the at least one word line during a floating time. A page buffer circuit is connected with the cell strings through bit lines. The page buffer senses voltage changes of the bit lines after the at least one word line is floated during the floating time and outputs a page buffer signal as a sensing result. A counter counts a number of off-cells in response to the page buffer signal. A detecting circuit outputs a detection signal associated with a defect cell based on the number of off-cells.

Abstract: Disclosed is a memory device which includes a memory cell array including memory cells, data latches connected with a sensing node and storing data in a first memory cell of the memory cells, a sensing latch connected with the sensing node, a temporary storage node, a switch connected between the sensing latch and the temporary storage node and configured to operate in response to a temporary storage node setup signal, a first precharge circuit configured to selectively precharge a first bit line corresponding to the first memory cell depending on a level of the temporary storage node, and a control logic circuit configured to control a dump operation between the data latches, the sensing latch, and the temporary storage node. The control logic circuit performs the dump operation from the data latches to the sensing latch while the first precharge circuit selectively precharges the first bit line.

Abstract: A non-volatile memory device includes: a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to selectively control the plurality of word lines, a page buffer including a plurality of latches corresponding to the plurality of bit lines, respectively, and a control circuit configured to control the non-volatile memory device to enter a suspend state after terminating a verify operation of a program loop of a program operation of the plurality of memory cells in response to a suspend request being generated during an execution operation of the program loop.

Abstract: A nonvolatile memory device includes a memory cell array having cell strings that each includes memory cells stacked on a substrate in a direction perpendicular to the substrate. A row decoder is connected with the memory cells through word lines. The row decoder applies a setting voltage to at least one word line of the word lines and floats the at least one word line during a floating time. A page buffer circuit is connected with the cell strings through bit lines. The page buffer senses voltage changes of the bit lines after the at least one word line is floated during the floating time and outputs a page buffer signal as a sensing result. A counter counts a number of off-cells in response to the page buffer signal. A detecting circuit outputs a detection signal associated with a defect cell based on the number of off-cells.

Abstract: A storage device including, a plurality of non-volatile memories configured to include a memory cell region including at least one first metal pad; and a peripheral circuit region including at least one second metal pad and vertically connected to the memory cell region by the at least one first metal pad and the at least one second metal pad, and a controller connected to the plurality of non-volatile memories through a plurality of channels and configured to control the plurality of non-volatile memories, wherein the controller selects one of a first read operation mode and a second read operation mode and transfers a read command corresponding to the selected read operation mode to the plurality of non-volatile memories, wherein one sensing operation is performed to identify one program state among program sates in the first read operation mode, and wherein at least two sensing operations are performed to identify the one program state among the program states in the second read operation mode.

Abstract: A storage device including, a plurality of non-volatile memories configured to include a memory cell region including at least one first metal pad; and a peripheral circuit region including at least one second metal pad and vertically connected to the memory cell region by the at least one first metal pad and the at least one second metal pad, and a controller connected to the plurality of non-volatile memories through a plurality of channels and configured to control the plurality of non-volatile memories, wherein the controller selects one of a first read operation mode and a second read operation mode and transfers a read command corresponding to the selected read operation mode to the plurality of non-volatile memories, wherein one sensing operation is performed to identify one program state among program sates in the first read operation mode, and wherein at least two sensing operations are performed to identify the one program state among the program states in the second read operation mode.

Abstract: A nonvolatile memory device includes a memory cell array having cell strings that each includes memory cells stacked on a substrate in a direction perpendicular to the substrate. A row decoder is connected with the memory cells through word lines. The row decoder applies a setting voltage to at least one word line of the word lines and floats the at least one word line during a floating time. A page buffer circuit is connected with the cell strings through bit lines. The page buffer senses voltage changes of the bit lines after the at least one word line is floated during the floating time and outputs a page buffer signal as a sensing result. A counter counts a number of off-cells in response to the page buffer signal. A detecting circuit outputs a detection signal associated with a defect cell based on the number of off-cells.

Abstract: A non-volatile memory device includes: a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to selectively control the plurality of word lines, a page buffer including a plurality of latches corresponding to the plurality of bit lines, respectively, and a control circuit configured to control the non-volatile memory device to enter a suspend state after terminating a verify operation of a program loop of a program operation of the plurality of memory cells in response to a suspend request being generated during an execution operation of the program loop.