Abstract: A spiral phase plate, according to one embodiment, for generating a Laguerre Gaussian beam by reflecting an incident beam emitted from a light source, may comprise: a first quadrant area in which the step height increase rate per unit angle decreases progressively in one direction from the point with the lowest step height to the point with the highest step height; and a second quadrant area in which the step height increase rate per unit angle increases progressively in the one direction.

Abstract: A smart card is provided. The smart card includes a peripheral circuit configured to control a fingerprint sensing array and generate a raw image, an authentication information processing module configured to process the raw image into fingerprint information for verification, a security module configured to determine whether the fingerprint information for verification matches registered fingerprint information to determine usage approval or disapproval for a payment request, and an active shield overlapping the security module. The peripheral circuit, the authentication information processing module, and the security module are integrated into one chip.

Abstract: An amplifying circuit may include: an amplifier configured to receive a first input voltage and output a first output voltage by amplifying the first input voltage; and a common-mode feedback circuit configured to enable the first output voltage to operate in a common mode by receiving the first output voltage and performing a feedback to adjust at least one feedback voltage applied to the amplifier based on the first output voltage. The common-mode feedback circuit may include a first Miller compensation circuit configured to perform dominant pole compensation by using a Miller effect for the common-mode feedback circuit. The first Miller compensation circuit may include a resistor and a capacitor.

Abstract: Provided is a current-to-voltage converter for converting a current signal into a voltage signal. The current-to-voltage converter may include: a trans-impedance amplifier including an input terminal and an output terminal; a resistor-capacitor (RC) circuit including a first end and a second end respectively connected to the input terminal and the output terminal of the trans-impedance amplifier, and a resistor and a capacitor connected to each other in parallel between the first end and the second end; and a plurality of switches configured to form at least one of a first converting circuit configured to convert the current signal via the trans-impedance amplifier and the RC circuit in a wide bandwidth mode, and a second converting circuit configured to convert the current signal via the RC circuit in a narrow bandwidth mode.

Abstract: Provided is a current-to-voltage converter for converting a current signal into a voltage signal. The current-to-voltage converter may include: a trans-impedance amplifier including an input terminal and an output terminal; a resistor-capacitor (RC) circuit including a first end and a second end respectively connected to the input terminal and the output terminal of the trans-impedance amplifier, and a resistor and a capacitor connected to each other in parallel between the first end and the second end; and a plurality of switches configured to form at least one of a first converting circuit configured to convert the current signal via the trans-impedance amplifier and the RC circuit in a wide bandwidth mode, and a second converting circuit configured to convert the current signal via the RC circuit in a narrow bandwidth mode.

Abstract: An amplifying circuit may include: an amplifier configured to receive a first input voltage and output a first output voltage by amplifying the first input voltage; and a common-mode feedback circuit configured to enable the first output voltage to operate in a common mode by receiving the first output voltage and performing a feedback to adjust at least one feedback voltage applied to the amplifier based on the first output voltage. The common-mode feedback circuit may include a first Miller compensation circuit configured to perform dominant pole compensation by using a Miller effect for the common-mode feedback circuit. The first Miller compensation circuit may include a resistor and a capacitor.

Abstract: An IC device includes a substrate including a device region having a fin-type active region and a deep trench region; a gate line that extends in a direction intersecting the fin-type active region; and an inter-device isolation layer that fills the deep trench region. The gate line includes a first gate portion that extends on the device region to cover the fin-type active region and has a flat upper surface at a first level and a second gate portion that extends on the deep trench region to cover the inter-device isolation layer while being integrally connected to the first gate portion and has an upper surface at a second level that is closer to the substrate than the first level.

Abstract: A dual-mode switching D.C.-to-D.C. converter includes a power conversion unit and a switch driver. The power conversion unit generates a D.C. output voltage based on a switch driving signal and a D.C. input voltage. The switch driver performs frequency compensation on the D.C. output voltage to generate a feedback voltage, and compares the feedback voltage with a comparison input signal to generate a pulse-width-modulated signal. The switch driver compares the D.C. output voltage with a first reference voltage to generate a comparison output signal. The switch driver generates the switch driving signal based on the pulse-width-modulated signal in a normal operation mode, and generates the switch driving signal based on the comparison output signal in an abnormal operation mode. The normal operation mode and the abnormal operation mode are based on a load current flowing through a load connected to the switching D.C.-to-D.C. converter.

Abstract: An IC device includes a substrate including a device region having a fin-type active region and a deep trench region; a gate line that extends in a direction intersecting the fin-type active region; and an inter-device isolation layer that fills the deep trench region. The gate line includes a first gate portion that extends on the device region to cover the fin-type active region and has a flat upper surface at a first level and a second gate portion that extends on the deep trench region to cover the inter-device isolation layer while being integrally connected to the first gate portion and has an upper surface at a second level that is closer to the substrate than the first level.

Abstract: An IC device includes a substrate including a device region having a fin-type active region and a deep trench region; a gate line that extends in a direction intersecting the fin-type active region; and an inter-device isolation layer that fills the deep trench region. The gate line includes a first gate portion that extends on the device region to cover the fin-type active region and has a flat upper surface at a first level and a second gate portion that extends on the deep trench region to cover the inter-device isolation layer while being integrally connected to the first gate portion and has an upper surface at a second level that is closer to the substrate than the first level.

Abstract: An IC device includes a substrate including a device region having a fin-type active region and a deep trench region; a gate line that extends in a direction intersecting the fin-type active region; and an inter-device isolation layer that fills the deep trench region. The gate line includes a first gate portion that extends on the device region to cover the fin-type active region and has a flat upper surface at a first level and a second gate portion that extends on the deep trench region to cover the inter-device isolation layer while being integrally connected to the first gate portion and has an upper surface at a second level that is closer to the substrate than the first level.

Abstract: Example embodiments disclose transistors and electronic devices including the transistors. A transistor may include a charge blocking layer between a gate insulating layer and a gate. An energy barrier between the gate insulating layer and the gate may be increased by the charge blocking layer. The transistor may be an oxide transistor including a channel layer formed of an oxide semiconductor.

Abstract: A dual-mode switching D.C.-to-D.C. converter includes a power conversion unit and a switch driver. The power conversion unit generates a D.C. output voltage based on a switch driving signal and a D.C. input voltage. The switch driver performs frequency compensation on the D.C. output voltage to generate a feedback voltage, and compares the feedback voltage with a comparison input signal to generate a pulse-width-modulated signal. The switch driver compares the D.C. output voltage with a first reference voltage to generate a comparison output signal. The switch driver generates the switch driving signal based on the pulse-width-modulated signal in a normal operation mode, and generates the switch driving signal based on the comparison output signal in an abnormal operation mode. The normal operation mode and the abnormal operation mode are based on a load current flowing through a load connected to the switching D.C.-to-D.C. converter.

Abstract: A semiconductor device including, a slope signal generator configured to generate a slope signal, an error signal generator configured to generate an error signal in response to an output voltage, a pulse width modulation (PWM) signal generator configured to generate a PWM signal using a difference between the slope signal and the error signal, and a slope signal controller configured to adjust the slope signal according to a difference between the output voltage and a reference voltage.

Abstract: An analog-to-digital conversion method using an RC time constant calibrator is provided. The method includes the operations of comparing a crossing time point at which a first reference signal and a second reference signal cross each other with a target time point and calibrating an RC time constant according to a result of the comparison. A length of time until the crossing time point at which a first analog signal and a second analog signal cross each other is counted based on a calibrated RC time constant. The counted value is output.

Abstract: Example embodiments disclose transistors and electronic devices including the transistors. A transistor may include a charge blocking layer between a gate insulating layer and a gate. An energy barrier between the gate insulating layer and the gate may be increased by the charge blocking layer. The transistor may be an oxide transistor including a channel layer formed of an oxide semiconductor.

Abstract: An analog-to-digital conversion method using an RC time constant calibrator is provided. The method includes the operations of comparing a crossing time point at which a first reference signal and a second reference signal cross each other with a target time point and calibrating an RC time constant according to a result of the comparison. A length of time until the crossing time point at which a first analog signal and a second analog signal cross each other is counted based on a calibrated RC time constant. The counted value is output.