Patents by Inventor Ji-Soo Park

Ji-Soo Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020034868
    Abstract: A semiconductor device having a gate and a fabrication method therefor is disclosed, which can improve a thermal stability, has a low resistance, and assure an easy fabrication process. The fabrication method includes the steps of (1) forming a first insulating film and a conductive film on a semiconductor substrate, (2) patterning the first insulating film and a conductive film on a semiconductor substrate, (2) patterning the first insulating film and the conductive film, to form a gate, (3) forming a second insulating film thicker than the gate on an entire surface, (4) planarizing the second insulating film, to expose the gate, (5) depositing a refractory metal layer on an entire surface, (6 ) forming a silicide layer on an upper surface of the gate by heat treatment, and (7) etching the refractory metal layer and the second insulating film.
    Type: Application
    Filed: December 3, 2001
    Publication date: March 21, 2002
    Applicant: Hyundai Micro Electronics Co., Ltd.
    Inventors: Ji Soo Park, Dong Kyun Sohn
  • Publication number: 20020022367
    Abstract: A method for fabricating a semiconductor substrate includes forming a suicide layer at a predetermined portion of a semiconductor substrate, implanting two or more impurity ions before annealing, and forming an impurity region in the semiconductor substrate by annealing the silicide layer and by diffusing the impurity ions from the silicide layer into the semiconductor substrate. Accordingly, the present invention can improve reliability and performance of a semiconductor device by reducing dopant loss and leakage current of a PN junction in the substrate and by decreasing a sheet resistance of the silicide layer. The dose of the second implanter ions is about one hundred to one thousand times less than the dose of the first implanted ions.
    Type: Application
    Filed: November 5, 1999
    Publication date: February 21, 2002
    Inventors: JI SOO PARK, DONG KYUN SON
  • Patent number: 6342441
    Abstract: A method for fabricating a semiconductor substrate includes forming a silicide layer at a predetermined portion of a semiconductor substrate, implanting two or more impurity ions before annealing, and forming an impurity region in the semiconductor substrate by annealing the silicide layer and by diffusing the impurity ions from the silicide layer into the semiconductor substrate. Accordingly, the present invention can improve reliability and performance of a semiconductor device by reducing dopant loss and leakage current of a PN junction in the substrate and by decreasing a sheet resistance of the silicide layer. The dose of the second implanter ions is about one hundred to one thousand times less than the dose of the first implanted ions.
    Type: Grant
    Filed: November 5, 1999
    Date of Patent: January 29, 2002
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Ji Soo Park, Dong Kyun Son
  • Publication number: 20010006832
    Abstract: Method for fabricating a polycide dual gate in a semiconductor device fabricates a dual gate having polycide gate electrodes. The polycide can be a cobalt polycide, for example. The method can include forming polysilicon pattern layers on a first and a second regions of a semiconductor substrate, forming a blocking layer to expose top surfaces of the polysilicon pattern layers and mask the substrate, and forming a metal layer on an entire surface and then is annealed to form a gate electrode having a stack of the polysilicon pattern layer under a silicide layer. Impurity ions of opposite conductivities in the first and second regions can be respectively deposited and diffused to form source/drain regions in surfaces of the substrate on both sides of the gate electrode. The implanted impurity ions can further implant ions in the silicide/polysilicon pattern layer gate to reduce fabrication steps or simplify the fabrication process.
    Type: Application
    Filed: December 14, 2000
    Publication date: July 5, 2001
    Applicant: Hyundai Electronics Industries Co., Ltd.
    Inventors: Jong Uk Bae, Ji Soo Park, Dong Kyun Sohn
  • Patent number: 6251780
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a refractory metal film on a semiconductor substrate, forming a capping film on the refractory metal film, injecting IV group atoms into the capping film to knock atoms of the capping film into the refractory metal film, and forming a metal silicide film at an interface between the semiconductor substrate and the refractory metal film.
    Type: Grant
    Filed: March 13, 2000
    Date of Patent: June 26, 2001
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Dong Kyun Sohn, Ji Soo Park, Jong Uk Bae
  • Patent number: 6177335
    Abstract: The method of forming a polycide that includes the steps of forming an insulating layer on a substrate, forming a first semiconductor layer on the insulating layer and forming a metal-ion buried layer in the first semiconductor layer; wherein the metal-ion buried layer is formed to be located to a predetermined depth from an upper surface of the first semiconductor layer. An impurity-ion buried layer is formed under the metal-ion buried layer in the first semiconductor layer such that the impurity-ion buried layer makes the first conductive layer electrically-conductive. A silicide layer and a conductive second semiconductor layer are formed by carrying out thermal treatment on the metal-ion buried layer and the impurity-ion buried layer.
    Type: Grant
    Filed: March 9, 2000
    Date of Patent: January 23, 2001
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Ji-Soo Park, Dong-Kyun Sohn