Abstract: A cylindrical secondary battery module includes: a plurality of cylindrical secondary battery cells respectively having a battery case in which an electrode assembly and an electrolyte are accommodated; a cell frame at which the plurality of cylindrical secondary battery cells are disposed; and a lid coupled to the cell frame and having a flame outlet. The cell frame includes: a plurality of plate members bent and coupled to intersect each other; and a space formed between the plurality of plate members so that the cylindrical secondary battery cells are disposed therein.

Abstract: The present invention provides a pharmaceutical composition for prevention or treatment of a stress disease and depression, the pharmaceutical composition be safely useable without toxicity and side effects by using an extract of leaves of Vaccinium bracteatum Thunb., which is natural resource of Korea, so that the reduction of manufacturing and production costs and the import substitution and export effects can be expected through the replacement of a raw material for preparation with a plant inhabiting in nature.

Abstract: Disclosed is a case for a battery module including a body having an internal space; and an end plate disposed on an end of the body, wherein the body includes a bottom plate on which a coolant flow path through which a coolant flows is formed, and wherein the end plate includes a coolant flow tube through which the coolant flows and a connection portion extending from the coolant flow tube and coupled to the coolant flow path.

Abstract: A semiconductor device includes a substrate including NMOS and PMOS regions; first and second active patterns on the NMOS region; third and fourth active patterns on the PMOS region, the third active pattern being spaced apart from the first active pattern; a first dummy gate structure on the first and third active patterns; a second dummy gate structure on the second and fourth active patterns; a normal gate structure on the third active pattern; a first source/drain pattern on the third active pattern and between the normal gate structure and the first dummy gate structure; and a first element separation structure between the first and second dummy gate structures and separating the third and fourth active patterns, wherein the first dummy gate structure includes a first dummy insulation gate intersecting the third active pattern.

Abstract: A semiconductor device includes first to sixth active patterns extending in a first direction and spaced apart in the first direction and a second direction; a field insulating layer between the first and second active patterns, an upper surface thereof being lower than upper surfaces of the first and second active patterns; a first gate structure on the field insulating layer and the first active pattern and extending in the second direction; a second gate structure on the field insulating layer and the second active pattern and extending in the second direction; a first separation trench extending between the second and third active patterns and the fifth and sixth active patterns, and a second separation trench extending between the first and second gate structures, wherein a lowest surface of the first separation trench is higher than a lowest surface of the second separation trench.

Abstract: Provided are a security processor for performing a remainder operation by using a random number and an operating method of the security processor. The security processor includes a random number generator configured to generate a first random number; a modular calculator configured to generate a first random operand based on first data and the first random number and generate output data through a remainder operation on the first random operand, wherein a result value of the remainder operation on the first input data is identical to a result value of the remainder operation on the first random operand.

Abstract: An encryption circuit includes a pipelined encryption core having a plurality of round cores therein. The pipelined encryption core is configured to perform a real round operation on each of a plurality of pieces of input data received therein and generate encryption data from the input data using an encryption operation comprising the real round operation. An encryption controller is provided, which is coupled to the pipelined encryption core. The encryption controller is configured to control the pipelined encryption core so that at least one of the plurality of round cores performs a virtual round operation as part of the encryption operation. The pipelined encryption core is configured to perform a virtual encryption operation using at least one of: (i) dummy data, and (ii) a dummy encryption key.

Abstract: A semiconductor device includes a substrate including NMOS and PMOS regions; first and second active patterns on the NMOS region; third and fourth active patterns on the PMOS region, the third active pattern being spaced apart from the first active pattern; a first dummy gate structure on the first and third active patterns; a second dummy gate structure on the second and fourth active patterns; a normal gate structure on the third active pattern; a first source/drain pattern on the third active pattern and between the normal gate structure and the first dummy gate structure; and a first element separation structure between the first and second dummy gate structures and separating the third and fourth active patterns, wherein the first dummy gate structure includes a first dummy insulation gate intersecting the third active pattern.

Abstract: A method of testing using a memory test apparatus connected to a memory device includes receiving a test command. When the test command is a finite state machine (FSM) operation command, the memory device is tested in accordance with the FSM operation command, and an operation is performed to output a result depending on a pass/fail result. But, when the test command is a direct access command, an auto-operation test of input data is performed in a test region according to received address information, and a test result is output, which may include output data with fail information or the auto-operation.

Abstract: A security device providing a security function for an image, a camera device including the same, and a system on chip (SOC) for controlling the camera device are provided. An image transmitting device may include an image processor configured to process an image to be transmitted to an external device, and a security circuit including a key shared with the external device. The security circuit may be configured to generate a tag used for image authentication by using data of a partial region of the image and the key based on region information for selecting the partial region of the image. The image transmitting device may be configured to transmit the tag, generated to correspond to the image, to the external device with data of the image.

Abstract: A semiconductor device includes a substrate including NMOS and PMOS regions; first and second active patterns on the NMOS region; third and fourth active patterns on the PMOS region, the third active pattern being spaced apart from the first active pattern; a first dummy gate structure on the first and third active patterns; a second dummy gate structure on the second and fourth active patterns; a normal gate structure on the third active pattern; a first source/drain pattern on the third active pattern and between the normal gate structure and the first dummy gate structure; and a first element separation structure between the first and second dummy gate structures and separating the third and fourth active patterns, wherein the first dummy gate structure includes a first dummy insulation gate intersecting the third active pattern.

Abstract: A semiconductor device includes first to sixth active patterns extending in a first direction and spaced apart in the first direction and a second direction; a field insulating layer between the first and second active patterns, an upper surface thereof being lower than upper surfaces of the first and second active patterns; a first gate structure on the field insulating layer and the first active pattern and extending in the second direction; a second gate structure on the field insulating layer and the second active pattern and extending in the second direction; a first separation trench extending between the second and third active patterns and the fifth and sixth active patterns, and a second separation trench extending between the first and second gate structures, wherein a lowest surface of the first separation trench is higher than a lowest surface of the second separation trench.

Abstract: A semiconductor device includes a substrate including NMOS and PMOS regions; first and second active patterns on the NMOS region; third and fourth active patterns on the PMOS region, the third active pattern being spaced apart from the first active pattern; a first dummy gate structure on the first and third active patterns; a second dummy gate structure on the second and fourth active patterns; a normal gate structure on the third active pattern; a first source/drain pattern on the third active pattern and between the normal gate structure and the first dummy gate structure; and a first element separation structure between the first and second dummy gate structures and separating the third and fourth active patterns, wherein the first dummy gate structure includes a first dummy insulation gate intersecting the third active pattern.

Abstract: An encryption device for performing virtual and real operations and a method of operating the encryption device. The method includes performing a virtual operation; when a real operation request signal is received, determining whether the virtual operation being performed is completed; and in response to the virtual operation being completed, performing a real operation in response to the real operation request signal.

Abstract: A method of testing using a memory test apparatus connected to a memory device includes receiving a test command. When the test command is a finite state machine (FSM) operation command, the memory device is tested in accordance with the FSM operation command, and an operation is performed to output a result depending on a pass/fail result. But, when the test command is a direct access command, an auto-operation test of input data is performed in a test region according to received address information, and a test result is output, which may include output data with fail information or the auto-operation.

Abstract: An authentication apparatus, included in a device supporting a network communication, includes a certificate handler that receives a certificate of an opponent and parses or verifies the certificate of the opponent. Cryptographic primitives receive an authentication request of the opponent, generate a random number in response to the authentication request, generate a challenge corresponding to the random number, and verify a response of the opponent corresponding to the challenge. A shared memory stores the parsed certificate, the random number, the challenge, and the response. An authentication controller controls the certificate handler, the cryptographic primitives, and the shared memory through a register setting, according to an authentication protocol.

Abstract: An application processor includes a security processor. An operating method of the security processor includes generating a recoder input including a digit-unit multiplier and a reference bit. At least one random bits having a random value are generated. When the recoder input has a predetermined pattern, the recoder input is converted into a first recoding value or a second recoding value according to a random bit corresponding to the recoder input to generate a recoding result.

Abstract: An encryption circuit includes a pipelined encryption core having a plurality of round cores therein. The pipelined encryption core is configured to perform a real round operation on each of a plurality of pieces of input data received therein and generate encryption data from the input data using an encryption operation comprising the real round operation. An encryption controller is provided, which is coupled to the pipelined encryption core. The encryption controller is configured to control the pipelined encryption core so that at least one of the plurality of round cores performs a virtual round operation as part of the encryption operation. The pipelined encryption core is configured to perform a virtual encryption operation using at least one of: (i) dummy data, and (ii) a dummy encryption key.

Abstract: An encryption device for performing virtual and real operations and a method of operating the encryption device. The method includes performing a virtual operation; when a real operation request signal is received, determining whether the virtual operation being performed is completed; and in response to the virtual operation being completed, performing a real operation in response to the real operation request signal.

Abstract: A security device providing a security function for an image, a camera device including the same, and a system on chip (SOC) for controlling the camera device are provided. An image transmitting device may include an image processor configured to process an image to be transmitted to an external device, and a security circuit including a key shared with the external device. The security circuit may be configured to generate a tag used for image authentication by using data of a partial region of the image and the key based on region information for selecting the partial region of the image. The image transmitting device may be configured to transmit the tag, generated to correspond to the image, to the external device with data of the image.