Abstract: An organic light-emitting display device includes: a plurality of pixels arranged in a matrix, wherein each of the pixels includes: an organic light emitting element; a first transistor including a gate electrode coupled to a scan line, a first electrode coupled to a data line, and a second electrode coupled to a first node, a second transistor configured to drive the organic light emitting element according to a data voltage provided through the first transistor; a third transistor including a first electrode coupled to the first node and a second electrode coupled to a second node; a first capacitor between the first node and a third node configured to have an initialization voltage applied; and a second capacitor between a fourth node coupled to a gate electrode of the second transistor and the second node.

Abstract: A display device includes a plurality of pixel columns, a plurality of switching units, a number of which corresponds to a number of the pixel columns, and a plurality of data lines of which a number is one more than the number of the pixel columns, where each of the switching units includes a first switch which transfers a data voltage to a first data line to which some of a plurality of pixels included in a corresponding pixel column are connected, and a second switch which transfers a data voltage to a second data line to which the other of the pixels included in the corresponding pixel column are connected, and a second switch included in a first switching unit among the switching units is connected with a first switch included in a second switching unit adjacent to the first switching unit.

Abstract: A scan driving circuit includes a plurality of stages, each having a shift register and a scan signal output unit. The shift register has a first node to receive a first driving voltage according to a control signal and a second node to receive the first driving voltage according to a reset signal. The scan signal output unit outputs scan signals to respective scan lines. The scan signal output unit has a plurality of clock switches controlled according to a voltage of the first node and a plurality of switches controlled according to a voltage of the second node. The clock switches sequentially output clock signals to respective third nodes, which are connected to respective scan lines. The switches output a second driving voltage to the third nodes.

Abstract: A non-quadrangular display is disclosed. In one aspect, the display includes a plurality of first signal lines formed in a non-quadrangular display area and a DC voltage line formed in a peripheral area surrounding the non-quadrangular display area. At least one of the first signal lines crosses the DC voltage line in the peripheral area.

Abstract: A scan driver includes a plurality of scan driving blocks. Each of the scan driving blocks includes a first shift register including a plurality of driving transistors, the first shift register being configured to provide a first driving signal to a first driving node and to provide a second driving signal to a second driving node, a second shift register including a plurality of masking transistors, the second shift register being configured to provide a masking signal to a masking output node, and a buffer circuit including a plurality of buffer transistors, the buffer circuit being configured to provide scan signals. The buffer circuit outputs the scan signals that include the first pulse or the scan signals that include the first pulse and the second pulse based on the masking signal.

Abstract: A pixel circuit includes a first-transistor including gate-electrode receiving first emission control signal, first-electrode connected to ELVDD, and second-electrode connected to first node, a second-transistor including gate-electrode receiving second emission control signal, first-electrode, and second-electrode connected to second node, a third-transistor including gate-electrode connected to third node, first-electrode connected to first node, and second-electrode connected to first-electrode of the second-transistor, an OLED including anode connected to second node and cathode connected to ELVSS, a fourth-transistor including gate-electrode receiving bias scan signal, first-electrode connected to initialization voltage, and second-electrode connected to second node, a fifth-transistor including gate-electrode receiving bias scan signal, first-electrode connected to reference voltage, and second-electrode connected to third node, a sixth-transistor including gate-electrode receiving data scan signal, fir

Abstract: An emission driver includes light emission driving controllers that are electrically connected to light emission control lines. Each of the light emission driving controllers may include a first circuit block configured to provide a second voltage to a first node in response to a first clock signal and to output a first voltage as a light emission control signal based on a voltage at the first node and a second clock signal having a phase difference from a phase of the first clock signal; and a second circuit block configured to provide a synchronization signal to a second node in response to the first clock signal, to maintain a voltage at the second node using a metal-oxide-semiconductor (MOS) capacitor, and to pull down the light emission control signal to have the second voltage in response to the voltage at the second node.

Abstract: Provided are an organic light emitting display device and method for manufacturing the same. According to an aspect of the present inventive concept, an organic light emitting display device including: a substrate; a common power line, a first drain electrode, and a second drain electrode each disposed on the substrate; a semiconductor pattern layer connected to the common power line and the second drain electrode; a gate electrode overlapping the semiconductor pattern layer; and an anode electrode connected to the second drain electrode. The semiconductor pattern layer, the gate electrode and the first drain electrode all overlap.

Abstract: Provided are an organic light emitting display device and method for manufacturing the same. According to an aspect of the present inventive concept, an organic light emitting display device including: a substrate; a common power line, a first drain electrode, and a second drain electrode each disposed on the substrate; a semiconductor pattern layer connected to the common power line and the second drain electrode; a gate electrode overlapping the semiconductor pattern layer; and an anode electrode connected to the second drain electrode. The semiconductor pattern layer, the gate electrode and the first drain electrode all overlap.

Abstract: A display device includes: a first pixel including a display element, a pixel circuit to provide a driving signal to the display element, a first transistor to control a connection between the pixel circuit and the display element, and a second transistor to control a connection between the display element and a repair line; a second pixel including a repair circuit to provide the driving signal to the repair line; and a repair control element connected to first and second control lines that are connected to gate electrodes of the first and second transistors, respectively, and configured to control the first and second transistors according to a repair control signal provided by a controller.

Abstract: A scan driver is integrated to include multiple drivers in a peripheral area of a display. The drivers output gate, emission, and/or other signals for driving pixel circuits in the display based on one or more clock signals.

Abstract: A scan driver includes scan signal outputting circuits, at least one of the scan signal outputting circuits includes a driving circuit and a buffer circuit. The driving circuit includes driving transistors. The driving circuit provides first and second driving signals to first and second driving nodes, respectively by turning on or off the driving transistors in response to clock signals and a scan input signal. The buffer circuit includes buffer transistors. The buffer circuit outputs a scan signal at an output node by turning on or off the buffer transistors in response to the first and second driving signals. The at least one of the scan signal outputting circuits performs a back-biasing voltage applying operation on at least one of the driving transistors and the buffer transistors when the driving transistors and the buffer transistors are turned on or off.

Abstract: A scan driver includes a plurality of scan driving blocks. Each of the scan driving blocks includes a first shift register including a plurality of driving transistors, the first shift register being configured to provide a first driving signal to a first driving node and to provide a second driving signal to a second driving node, a second shift register including a plurality of masking transistors, the second shift register being configured to provide a masking signal to a masking output node, and a buffer circuit including a plurality of buffer transistors, the buffer circuit being configured to provide scan signals. The buffer circuit outputs the scan signals that include the first pulse or the scan signals that include the first pulse and the second pulse based on the masking signal.

Abstract: A pixel circuit includes a first-transistor including gate-electrode receiving first emission control signal, first-electrode connected to ELVDD, and second-electrode connected to first node, a second-transistor including gate-electrode receiving second emission control signal, first-electrode, and second-electrode connected to second node, a third-transistor including gate-electrode connected to third node, first-electrode connected to first node, and second-electrode connected to first-electrode of the second-transistor, an OLED including anode connected to second node and cathode connected to ELVSS, a fourth-transistor including gate-electrode receiving bias scan signal, first-electrode connected to initialization voltage, and second-electrode connected to second node, a fifth-transistor including gate-electrode receiving bias scan signal, first-electrode connected to reference voltage, and second-electrode connected to third node, a sixth-transistor including gate-electrode receiving data scan signal, fir

Abstract: A demultiplexer includes: a first transistor connected between a data input line and a first data output line; a second transistor connected between the data input line and a second data output line; and an initializing transistor configured to be simultaneously turned on with the first transistor to transmit an initializing voltage to the second data output line.

Abstract: An emission driver includes light emission driving controllers that are electrically connected to light emission control lines. Each of the light emission driving controllers may include a first circuit block configured to provide a second voltage to a first node in response to a first clock signal and to output a first voltage as a light emission control signal based on a voltage at the first node and a second clock signal having a phase difference from a phase of the first clock signal; and a second circuit block configured to provide a synchronization signal to a second node in response to the first clock signal, to maintain a voltage at the second node using a metal-oxide-semiconductor (MOS) capacitor, and to pull down the light emission control signal to have the second voltage in response to the voltage at the second node.

Abstract: A non-quadrangular display is disclosed. In one aspect, the display includes a plurality of first signal lines formed in a non-quadrangular display area and a DC voltage line formed in a peripheral area surrounding the non-quadrangular display area. At least one of the first signal lines crosses the DC voltage line in the peripheral area.

Abstract: A scan driving circuit includes a plurality of stages, each having a shift register and a scan signal output unit. The shift register has a first node to receive a first driving voltage according to a control signal and a second node to receive the first driving voltage according to a reset signal. The scan signal output unit outputs scan signals to respective scan lines. The scan signal output unit has a plurality of clock switches controlled according to a voltage of the first node and a plurality of switches controlled according to a voltage of the second node. The clock switches sequentially output clock signals to respective third nodes, which are connected to respective scan lines. The switches output a second driving voltage to the third nodes.

Abstract: A display device includes: a first pixel including a display element, a pixel circuit to provide a driving signal to the display element, a first transistor to control a connection between the pixel circuit and the display element, and a second transistor to control a connection between the display element and a repair line; a second pixel including a repair circuit to provide the driving signal to the repair line; and a repair control element connected to first and second control lines that are connected to gate electrodes of the first and second transistors, respectively, and configured to control the first and second transistors according to a repair control signal provided by a controller.

Abstract: An organic light-emitting display device includes: a plurality of pixels arranged in a matrix, wherein each of the pixels includes: an organic light emitting element; a first transistor including a gate electrode coupled to a scan line, a first electrode coupled to a data line, and a second electrode coupled to a first node, a second transistor configured to drive the organic light emitting element according to a data voltage provided through the first transistor; a third transistor including a first electrode coupled to the first node and a second electrode coupled to a second node; a first capacitor between the first node and a third node configured to have an initialization voltage applied; and a second capacitor between a fourth node coupled to a gate electrode of the second transistor and the second node.